docs/spec-compiler-part-3-mem.md

not measured20highlighted source passages6/6PBTs with runs24draft PRs

MS0V7 Selected stage: loom-lower-graph-memory. Te…MS1V2 Selected stage: loom-lower-graph-memory. Te…MS1V4 Selected stage: loom-lower-graph-memory. Te…MS1V7 Selected stage: loom-lower-graph-memory. Te…MS2V Selected stage: loom-lower-graph-memory. Te…MS2V3 Selected stage: loom-lower-graph-memory. Te…

Violation observedsuite result0.0%remaining-PBT confidence estimate5 considered · 1 missing

How combined confidence is computed

max(0, 1 − sum of PBT residual-risk estimates). Uses each distinct available PBT’s latest-run estimate and its own sampling scope; PBTs without estimates are reported and omitted. An observed violation remains the suite result; when other PBTs have estimates, their estimate is still shown. Assumes no independence. This is a combined point estimate, not a statistical confidence bound or deployment reliability. Uncovered passages are outside its scope.

Missing confidence evidence (omitted from the estimate):

Selected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at: violated

Code coverage+240lines+130branches9contributing files6/6PBTs measured

Coverage added over the baseline, grouped by PBT. Only files with gains appear below.

Source file	Baseline coverage	Baseline + input	Contributing input
`…/lib/Dataflow/IR/DataflowMemoryContracts.cpp`MS0V	198/371lines53.4% 98/218branches45.0%	221/371lines59.6%+23 116/218branches53.2%+18	+23 lines · +18 branchesseed 38 · 12 → 11 linesOpen PBT Review PR
23 newly covered lines · 18 newly covered branches 105 `auto rmw = llvm::dyn_cast<AtomicRmwOp>(op);`106 `if (!rmw)`107 `return llvm::isa<CmpXchgOp>(op)`false branch108 `? AtomicElementCategory::Integer`109 `: AtomicElementCategory::IntegerOrFloatingPoint;`⋮133 `const char required = "";`134 `switch (category) {`135 `case AtomicElementCategory::Integer:`false branch136 `if (isInteger)`137 `return llvm::Error::success();`⋮143 `required = "floating-point";`144 `break;`145 `case AtomicElementCategory::IntegerOrFloatingPoint:`true branch146 `if (isInteger \|\| isFloat)`true branch147 `return llvm::Error::success();`148 `required = "integer or floating-point";`149 `break;`⋮255`llvm::Error validateSingleContractOwner(Operation op) {`256 `for (NamedAttribute attribute : op->getAttrs()) {`257 `if (attribute.getName() == "contract")`false branch258 `continue;`259 `llvm::StringRef name = attribute.getName().strref();`260 `if (llvm::isa<PlainAccessContractAttr, AtomicAccessContractAttr,`false branch261 `AtomicRmwContractAttr, CompareExchangeContractAttr,`262 `FenceContractAttr>(attribute.getValue()))`263 `return contractError("'" + name +`264 `"' must not carry a second aggregate memory "`265 `"contract");`266 `if (llvm::isa<SyncScopeRefAttr>(attribute.getValue()))`false branch267 `return contractError("'" + name +`268 `"' must not carry a second synchronization scope");`269 `}`270 `return llvm::Error::success();`271`}`⋮289290`/// The orderings an atomic store rejects.`291`bool isAcquireOrAcqRel(AtomicOrdering ordering) {`292 `return ordering == AtomicOrdering::Acquire \|\|`false branch293 `ordering == AtomicOrdering::AcqRel;`false branch294`}`295296/// `source_alignment_bytes` is identity-critical typed state and must be a⋮390 `aggregate = PlainAccessContractAttr::get(typedOp.getContext(),`391 `/is_volatile=/false);`392 `if (auto plain = llvm::dyn_cast<PlainAccessContractAttr>(aggregate))`false branch393 `return MemoryActorContract{`394 `aggregate, /atomic=/false, plain.getIsVolatile(),`395 `std::nullopt, std::nullopt, SyncScopeRefAttr()};`396 `auto access = llvm::cast<AtomicAccessContractAttr>(aggregate);`397 `return MemoryActorContract{aggregate,`398 `/atomic=/true,`399 `access.getIsVolatile(),`400 `access.getSourceAlignmentBytes(),`401 `access.getVectorGranularity(),`402 `access.getSyncScope()};`403 `})`404 `.Case<AtomicRmwOp>([](AtomicRmwOp typedOp) {`⋮480 `// these. Duplicate effect kinds across the bound and unbound forms are`481 `// intentional.`482 `if (contract->atomic \|\| contract->isVolatile) {`true branch483 `effects.emplace_back(MemoryEffects::Read::get());`484 `effects.emplace_back(MemoryEffects::Write::get());`⋮498 `// Only dataflow.load and dataflow.store nest a bare atomic access contract,`499 `// and each rejects the orderings its direction cannot express.`500 `if (auto atomic =`true branch501 `llvm::dyn_cast<AtomicAccessContractAttr>(contract->aggregate)) {`502 `if (llvm::isa<LoadOp>(op) && isReleaseOrAcqRel(atomic.getOrdering()))`false branchfalse branchtrue branch503 `return contractError("atomic load ordering must not be 'release' or "`504 `"'acq_rel'");`505 `if (llvm::isa<StoreOp>(op) && isAcquireOrAcqRel(atomic.getOrdering()))`false branchfalse branchtrue branch506 `return contractError("atomic store ordering must not be 'acquire' or "`507 `"'acq_rel'");`508 `}`509 `if (auto rmw = llvm::dyn_cast<AtomicRmwOp>(op))`510 `if (rmw.getContract().getAccess().getOrdering() ==`
`…/lib/Dataflow/IR/DataflowActorSemantics.cpp`MS1V	1089/1621lines67.2% 747/1330branches56.2%	1110/1621lines68.5%+21 761/1330branches57.2%+14	+21 lines · +14 branchesseed 1 · 30 → 19 linesOpen PBT Review PR +21 lines · +14 branchesseed 1 · 30 → 28 linesOpen PBT Review PR
21 newly covered lines · 14 newly covered branches 1397 `std::errc::invalid_argument,`1398 `"mask is only valid for a vector memory access");`1399 `} else if (auto pointer =`false branch1400 `llvm::dyn_cast<mlir::LLVM::LLVMPointerType>(dataType)) {`1401 `if (maskType)`⋮1417 `"P(AS) bits");`1418 `access.dataPointerLayout = layout;`1419 `} else if (llvm::isa<mlir::VectorType>(dataType)) {`true branch1420 `auto vector = analyzeFixedRankDataVector(dataType, VectorRank::AnyFixed);`1421 `if (!vector)`false branch1422 `return vector.takeError();`1423 `if (vector->getElementType() != elementType)`false branch1424 `return llvm::createStringError(`1425 `std::errc::invalid_argument,`⋮1427 `typeToString(vector->getElementType()).c_str(),`1428 `typeToString(elementType).c_str());`1429 `if (maskType)`false branchtrue branch1430 `if (llvm::Error error = validateVectorMaskType(vector, maskType))`false branch1431 `return std::move(error);`1432 `access.vectorType = vector;`1433 `} else {`1434 `return llvm::createStringError(`1435 `std::errc::invalid_argument,`⋮1440 `return access;`14411442 `if (auto pointer = llvm::dyn_cast<mlir::LLVM::LLVMPointerType>(addressType)) {`false branch1443 `auto layout = loom::resolvePointerLayout(scope, pointer.getAddressSpace());`1444 `if (!layout)`⋮1449 `}`14501451 `auto addressVector = llvm::dyn_cast<mlir::VectorType>(addressType);`1452 `if (!addressVector)`false branch1453 `return llvm::createStringError(`1454 `std::errc::invalid_argument,`1455 `"operand #1 must be index, LLVM pointer, or a fixed-size vector of "`1456 `"one of those types");`1457 `if (addressVector.isScalable())`false branch1458 `return llvm::createStringError(std::errc::invalid_argument,`1459 `"address vector must be a fixed-size "`1460 `"vector");`1461 `const bool indexAddress =`1462 `llvm::isa<mlir::IndexType>(addressVector.getElementType());`1463 `auto pointerAddress = llvm::dyn_cast<mlir::LLVM::LLVMPointerType>(`1464 `addressVector.getElementType());`1465 `if (!indexAddress && !pointerAddress)`false branch1466 `return llvm::createStringError(std::errc::invalid_argument,`1467 `"address vector element type must be "`1468 `"'index' or an LLVM pointer");`1469 `if (!access.isVector())`false branch1470 `return llvm::createStringError(`1471 `std::errc::invalid_argument,`1472 `"vector address requires a fixed-size vector data type");`1473 `if (addressVector.getShape() != access.vectorType.getShape())`false branch1474 `return llvm::createStringError(`1475 `std::errc::invalid_argument,`⋮1477 `typeToString(addressVector).c_str(),`1478 `typeToString(access.vectorType).c_str());`1479 `access.addressVectorType = addressVector;`1480 `if (pointerAddress) {`false branch1481 `auto layout =`1482 `loom::resolvePointerLayout(scope, pointerAddress.getAddressSpace());`⋮1486 `access.pointerLayout = layout;`1487 `}`1488 `return access;`1489`}`14901491`llvm::Expected<dataflow::semantics::StreamTransition>`
`…/lib/Dataflow/IR/DataflowOps.cpp`MS1V	270/410lines65.9% 103/228branches45.2%	304/410lines74.1%+34 124/228branches54.4%+21	+34 lines · +21 branchesseed 1 · 30 → 19 linesOpen PBT Review PR +34 lines · +21 branchesseed 1 · 30 → 28 linesOpen PBT Review PR
34 newly covered lines · 21 newly covered branches 194 `types.addressType = parser.getBuilder().getIndexType();`195 `types.dataType = types.memoryType.getElementType();`196 `if (failed(parser.parseOptionalComma()))`false branch197 `return success();`198199 `Type firstExplicitType;`200 `if (parser.parseType(firstExplicitType))`false branch201 `return failure();`202 `auto isAddressType = [](Type type) {`203 `if (isa<IndexType, LLVM::LLVMPointerType>(type))`false branch204 `return true;`205 `auto vector = dyn_cast<VectorType>(type);`206 `return vector &&`true branch207 `isa<IndexType, LLVM::LLVMPointerType>(vector.getElementType());`true branch208 `};`209 `if (failed(parser.parseOptionalComma())) {`false branch210 `if (isAddressType(firstExplicitType))`211 `types.addressType = firstExplicitType;`⋮214 `return success();`215 `}`216 `if (!isAddressType(firstExplicitType))`false branch217 `return parser.emitError(parser.getCurrentLocation(),`218 `"first explicit type must be an address type");`219220 `types.addressType = firstExplicitType;`221 `return parser.parseType(types.dataType);`222`}`223224`FailureOr<VectorType> getParsedDataVector(OpAsmParser &parser, Type dataType) {`225 `auto vector = dyn_cast<VectorType>(dataType);`226 `if (!vector)`false branch227 `return parser.emitError(`228 `parser.getCurrentLocation(),`229 `"masked memory access requires an explicit vector data type");`230 `return vector;`231`}`232233`Type getMaskType(OpAsmParser &parser, VectorType dataVector) {`234 `return VectorType::get(dataVector.getShape(), parser.getBuilder().getI1Type(),`235 `dataVector.getScalableDims());`236`}`237238`bool hasExplicitMemoryDataType(Value memory, Type dataType) {`⋮240`}`241242`bool isMemoryAddressType(Type type) {`243 `if (isa<IndexType, LLVM::LLVMPointerType>(type))`false branch244 `return true;`245 `auto vector = dyn_cast<VectorType>(type);`246 `return vector &&`true branch247 `isa<IndexType, LLVM::LLVMPointerType>(vector.getElementType());`false branch248`}`249250`/// Parses the grammar shared by every addressed memory actor:`⋮270271 `bool hasMask = succeeded(parser.parseOptionalKeyword("mask"));`272 `if (hasMask && parser.parseOperand(mask))`false branchtrue branch273 `return failure();`274 `if (parser.parseOptionalAttrDict(result.attributes) \|\|`⋮282 `result.operands))`283 `return failure();`284 `if (hasMask) {`true branch285 `FailureOr<VectorType> vector = getParsedDataVector(parser, types.dataType);`286 `if (failed(vector) \|\|`false branchfalse branch287 `parser.resolveOperand(mask, getMaskType(parser, *vector),`false branch288 `result.operands))`289 `return failure();`290 `}`291 `return success();`292`}`⋮299 `printer << ' ' << value;`300 `printer << ' ' << control;`301 `if (mask)`true branch302 `printer << " mask " << mask;`303 `printer.printOptionalAttrDict(op->getAttrs());`304 `printer << " : " << memory.getType();`⋮308 `// unambiguous and round-trippable.`309 `if (!isa<IndexType>(address.getType()) \|\|`310 `(explicitData && isMemoryAddressType(dataType)))`false branchtrue branch311 `printer << ", " << address.getType();`312 `if (explicitData)`⋮321 `auto access = semantics::analyzeMemoryAccessType(`322 `cast<MemRefType>(memory.getType()), dataType, address.getType(), op,`323 `mask ? mask.getType() : Type{});`true branch324 `if (!access)`325 `return op->emitOpError(llvm::toString(access.takeError()));`
`…/lib/Dataflow/IR/DataflowVectorSemantics.cpp`MS1V	81/121lines66.9% 53/106branches50.0%	81/121lines66.9%+0 54/106branches50.9%+1	+1 branchseed 1 · 30 → 19 linesOpen PBT Review PR +1 branchseed 1 · 30 → 28 linesOpen PBT Review PR
1 newly covered branch 42 `auto vector = llvm::dyn_cast<mlir::VectorType>(type);`43 `const bool admitted = vector && !vector.isScalable() &&`44 `(rank == VectorRank::AnyFixed ? vector.getRank() > 0`true branch45 `: vector.getRank() == 1);`46 `if (!admitted)`
`…/lib/Frontend/Lowering/GraphRegionLowering.cpp`MS1V	1416/1626lines87.1% 532/680branches78.2%	1462/1626lines89.9%+46 540/680branches79.4%+8	+46 lines · +8 branchesseed 1 · 30 → 19 linesOpen PBT Review PR +46 lines · +8 branchesseed 1 · 30 → 28 linesOpen PBT Review PR
46 newly covered lines · 8 newly covered branches 167 `store, store.getMemRefType(), store.getIndices(), indexBits)))`168 `return ::mlir::WalkResult::interrupt();`169 `} else if (auto read =`true branch170 `::llvm::dyn_cast<::mlir::vector::TransferReadOp>(op)) {`171 `if (::mlir::failed(`false branch172 `::loom::lowering::detail::checkRankedVectorTransferRead(`173 `read, indexBits)))`174 `return ::mlir::WalkResult::interrupt();`175 `} else if (auto write =`true branch176 `::llvm::dyn_cast<::mlir::vector::TransferWriteOp>(op)) {`177 `if (::mlir::failed(`false branch178 `::loom::lowering::detail::checkRankedVectorTransferWrite(`179 `write, indexBits)))`180 `return ::mlir::WalkResult::interrupt();`181 `} else if (auto dealloc = ::llvm::dyn_cast<::mlir::memref::DeallocOp>(op)) {`⋮707 `if (auto store = ::llvm::dyn_cast<::mlir::memref::StoreOp>(op))`708 `return store.getMemref();`709 `if (auto read = ::llvm::dyn_cast<::mlir::vector::TransferReadOp>(op))`true branch710 `return read.getBase();`711 `if (auto write = ::llvm::dyn_cast<::mlir::vector::TransferWriteOp>(op))`true branch712 `return write.getBase();`713 `return {};`714 `}`⋮1144 `continue;`1145 `}`1146 `if (auto read = ::llvm::dyn_cast<::mlir::vector::TransferReadOp>(op)) {`true branch1147 `lowerVectorRead(read, execution, memory);`1148 `continue;`1149 `}`1150 `if (auto write = ::llvm::dyn_cast<::mlir::vector::TransferWriteOp>(op)) {`true branch1151 `lowerVectorWrite(write, execution, memory);`1152 `continue;`1153 `}`1154 `if (auto dealloc = ::llvm::dyn_cast<::mlir::memref::DeallocOp>(op)) {`1155 `dealloc.erase();`⋮13891390 `void lowerVectorRead(::mlir::vector::TransferReadOp read,`1391 `::mlir::Value execution, MemoryState &memory) {`1392 `::llvm::SmallVector<unsigned, 4> membership = partitionsFor(read);`1393 `::mlir::Value ctrl = readControl(read, execution, memory);`1394 `setInsertionPoint(read.getLoc());`1395 `auto memoryType =`1396 `::llvm::cast<::mlir::MemRefType>(read.getBase().getType());`1397 `::mlir::Value address = ::loom::lowering::detail::buildExactLinearIndex(`1398 `builder, read.getLoc(), memoryType, read.getIndices(), execution);`1399 `auto lowered = ::dataflow::LoadOp::create(`1400 `builder, read.getLoc(), read.getVectorType(), builder.getNoneType(),`1401 `read.getBase(), address, ctrl, read.getMask(), ::mlir::Attribute{});`1402 `partitionsByAccess.try_emplace(lowered, std::move(membership));`1403 `read.getResult().replaceAllUsesWith(lowered.getData());`1404 `updateReadFrontiers(lowered, lowered.getDone(), memory);`1405 `read.erase();`1406 `}`14071408 `void lowerVectorWrite(::mlir::vector::TransferWriteOp write,`1409 `::mlir::Value execution, MemoryState &memory) {`1410 `::llvm::SmallVector<unsigned, 4> membership = partitionsFor(write);`1411 `::mlir::Value ctrl = writeControl(write, execution, memory);`1412 `setInsertionPoint(write.getLoc());`1413 `auto memoryType =`1414 `::llvm::cast<::mlir::MemRefType>(write.getBase().getType());`1415 `::mlir::Value address = ::loom::lowering::detail::buildExactLinearIndex(`1416 `builder, write.getLoc(), memoryType, write.getIndices(), execution);`1417 `auto lowered = ::dataflow::StoreOp::create(`1418 `builder, write.getLoc(), builder.getNoneType(), write.getBase(),`1419 `address, write.getValueToStore(), ctrl, write.getMask(),`1420 `::mlir::Attribute{});`1421 `partitionsByAccess.try_emplace(lowered, std::move(membership));`1422 `updateWriteFrontiers(lowered, lowered.getDone(), memory);`1423 `write.erase();`1424 `}`14251426 `void lowerDataflowLoad(::dataflow::LoadOp load, ::mlir::Value execution,`
`…/lib/Frontend/Lowering/RankedMemRefLowering.cpp`MS1V	60/133lines45.1% 27/94branches28.7%	106/133lines79.7%+46 54/94branches57.4%+27	+46 lines · +27 branchesseed 1 · 30 → 19 linesOpen PBT Review PR +46 lines · +27 branchesseed 1 · 30 → 28 linesOpen PBT Review PR
46 newly covered lines · 27 newly covered branches 17`namespace {`1819`bool allTransferDimensionsInBounds(::mlir::ArrayAttr attribute) {`20 `return attribute && ::llvm::all_of(attribute, [](::mlir::Attribute value) {`true branchtrue branch21 `return ::llvm::cast<::mlir::BoolAttr>(value).getValue();`22 `});`23`}`2425`bool resultIsMaskGuarded(::mlir::vector::TransferReadOp read) {`26 `::mlir::Value mask = read.getMask();`27 `return mask && !read.getResult().use_empty() &&`true branchtrue branch28 `::llvm::all_of(`false branch29 `read.getResult().getUsers(), [&](::mlir::Operation user) {`30 `auto select = ::llvm::dyn_cast<::mlir::arith::SelectOp>(user);`31 `return select && select.getCondition() == mask &&`false branch32 `select.getTrueValue() == read.getResult() &&`33 `select.getFalseValue() != read.getResult();`34 `});`35`}`3637`::mlir::LogicalResult checkRankedVectorTransfer(::mlir::Operation operation,`⋮41 `::mlir::AffineMap permutation,`42 `::mlir::ArrayAttr inBounds,`43 `unsigned indexBits) {`44 `::llvm::SmallVector<std::int64_t> strides;`45 `std::int64_t offset = 0;`46 `if (vector.isScalable() \|\| vector.getRank() != 1 \|\| memory.getRank() != 1 \|\|`false branchfalse branchfalse branchfalse branch47 `memory.getElementType() != vector.getElementType() \|\|`false branch48 `::mlir::failed(memory.getStridesAndOffset(strides, offset)) \|\|`false branch49 `strides.size() != 1 \|\| strides.front() != 1 \|\|`false branchfalse branch50 `permutation !=`false branch51 `::mlir::AffineMap::getMultiDimIdentityMap(1, operation->getContext()))`52 `return operation->emitError(`53 `"loom-lower-graph-memory: vector transfer requires a fixed rank-one "`54 `"minor-identity access over a unit-stride scalar memref");`55 `if (!allTransferDimensionsInBounds(inBounds))`false branch56 `return operation->emitError(`57 `"loom-lower-graph-memory: vector transfer requires every lane to be "`58 `"proven in-bounds");`59 `return checkRankedMemRefAccess(operation, memory, indices, indexBits);`60`}`6162`} // namespace`⋮115`::mlir::LogicalResult`116`checkRankedVectorTransferRead(::mlir::vector::TransferReadOp read,`117 `unsigned indexBits) {`118 `auto memory = ::llvm::dyn_cast<::mlir::MemRefType>(read.getBase().getType());`119 `if (!memory)`false branch120 `return read.emitOpError(`121 `"loom-lower-graph-memory: vector read requires a ranked memref base");`122 `const bool paddingCanBeObserved =`123 `read.getMask() && !resultIsMaskGuarded(read);`true branchfalse branchtrue branch124 `if (paddingCanBeObserved &&`false branchtrue branchfalse branch125 `!::mlir::matchPattern(read.getPadding(), ::mlir::m_Zero()))`false branch126 `return read.emitOpError(`127 `"loom-lower-graph-memory: observable vector read padding must be "`128 `"zero");`129 `return checkRankedVectorTransfer(`130 `read, memory, read.getIndices(), read.getVectorType(),`131 `read.getPermutationMap(), read.getInBounds(), indexBits);`132`}`133134`::mlir::LogicalResult`135`checkRankedVectorTransferWrite(::mlir::vector::TransferWriteOp write,`136 `unsigned indexBits) {`137 `auto memory = ::llvm::dyn_cast<::mlir::MemRefType>(write.getBase().getType());`138 `if (!memory \|\| write.getResult())`false branchfalse branchfalse branch139 `return write.emitOpError(`140 `"loom-lower-graph-memory: vector write requires a ranked memref base");`141 `return checkRankedVectorTransfer(`142 `write, memory, write.getIndices(), write.getVectorType(),`143 `write.getPermutationMap(), write.getInBounds(), indexBits);`144`}`145146`::mlir::Value buildExactLinearIndex(::mlir::OpBuilder &builder,`
`…/lib/Dataflow/IR/DataflowMemoryContracts.cpp`MS1V	198/371lines53.4% 98/218branches45.0%	234/371lines63.1%+36 123/218branches56.4%+25	+4 lines · +3 branchesseed 207 · 20 → 17 linesOpen PBT Review PR +21 lines · +14 branchesseed 3 · 19 → 19 linesOpen PBT Review PR +23 lines · +15 branchesseed 40 · 19 → 18 linesOpen PBT Review PR +22 lines · +18 branchesseed 528 · 21 → 21 linesOpen PBT Review PR +22 lines · +18 branchesseed 1608 · 21 → 21 linesOpen PBT Review PR +6 lines · +4 branchesseed 1617 · 20 → 19 linesOpen PBT Review PR +2 lines · +2 branchesseed 2 · 15 → 15 linesOpen PBT Review PR +4 lines · +3 branchesseed 207 · 20 → 19 linesOpen PBT Review PR +21 lines · +17 branchesseed 2249 · 20 → 20 linesOpen PBT Review PR +22 lines · +15 branchesseed 2449 · 20 → 20 linesOpen PBT Review PR +6 lines · +4 branchesseed 2631 · 18 → 18 linesOpen PBT Review PR
36 newly covered lines · 25 newly covered branches 45`llvm::AtomicRMWInst::BinOp toLLVMBinOp(AtomicRmwKind kind) {`46 `switch (kind) {`47 `case AtomicRmwKind::Xchg:`true branch48 `return llvm::AtomicRMWInst::Xchg;`49 `case AtomicRmwKind::Add:`false branch50 `return llvm::AtomicRMWInst::Add;`51 `case AtomicRmwKind::Sub:`true branch52 `return llvm::AtomicRMWInst::Sub;`53 `case AtomicRmwKind::And:`true branch54 `return llvm::AtomicRMWInst::And;`55 `case AtomicRmwKind::Nand:`56 `return llvm::AtomicRMWInst::Nand;`57 `case AtomicRmwKind::Or:`true branch58 `return llvm::AtomicRMWInst::Or;`59 `case AtomicRmwKind::Xor:`true branch60 `return llvm::AtomicRMWInst::Xor;`61 `case AtomicRmwKind::Max:`true branch62 `return llvm::AtomicRMWInst::Max;`63 `case AtomicRmwKind::Min:`true branch64 `return llvm::AtomicRMWInst::Min;`65 `case AtomicRmwKind::UMax:`true branch66 `return llvm::AtomicRMWInst::UMax;`67 `case AtomicRmwKind::UMin:`true branch68 `return llvm::AtomicRMWInst::UMin;`69 `case AtomicRmwKind::FAdd:`70 `return llvm::AtomicRMWInst::FAdd;`⋮105 `auto rmw = llvm::dyn_cast<AtomicRmwOp>(op);`106 `if (!rmw)`107 `return llvm::isa<CmpXchgOp>(op)`false branch108 `? AtomicElementCategory::Integer`109 `: AtomicElementCategory::IntegerOrFloatingPoint;`110 `llvm::AtomicRMWInst::BinOp binOp = toLLVMBinOp(rmw.getContract().getKind());`111 `if (binOp == llvm::AtomicRMWInst::Xchg)`true branch112 `return AtomicElementCategory::IntegerOrFloatingPoint;`113 `return llvm::AtomicRMWInst::isFPOperation(binOp)`114 `? AtomicElementCategory::FloatingPoint`⋮133 `const char required = "";`134 `switch (category) {`135 `case AtomicElementCategory::Integer:`false branch136 `if (isInteger)`137 `return llvm::Error::success();`⋮143 `required = "floating-point";`144 `break;`145 `case AtomicElementCategory::IntegerOrFloatingPoint:`true branch146 `if (isInteger \|\| isFloat)`true branch147 `return llvm::Error::success();`148 `required = "integer or floating-point";`149 `break;`⋮289290`/// The orderings an atomic store rejects.`291`bool isAcquireOrAcqRel(AtomicOrdering ordering) {`292 `return ordering == AtomicOrdering::Acquire \|\|`false branch293 `ordering == AtomicOrdering::AcqRel;`false branch294`}`295296/// `source_alignment_bytes` is identity-critical typed state and must be a⋮390 `aggregate = PlainAccessContractAttr::get(typedOp.getContext(),`391 `/is_volatile=/false);`392 `if (auto plain = llvm::dyn_cast<PlainAccessContractAttr>(aggregate))`false branch393 `return MemoryActorContract{`394 `aggregate, /atomic=/false, plain.getIsVolatile(),`395 `std::nullopt, std::nullopt, SyncScopeRefAttr()};`396 `auto access = llvm::cast<AtomicAccessContractAttr>(aggregate);`397 `return MemoryActorContract{aggregate,`398 `/atomic=*/true,`399 `access.getIsVolatile(),`400 `access.getSourceAlignmentBytes(),`401 `access.getVectorGranularity(),`402 `access.getSyncScope()};`403 `})`404 `.Case<AtomicRmwOp>([](AtomicRmwOp typedOp) {`⋮498 `// Only dataflow.load and dataflow.store nest a bare atomic access contract,`499 `// and each rejects the orderings its direction cannot express.`500 `if (auto atomic =`true branch501 `llvm::dyn_cast<AtomicAccessContractAttr>(contract->aggregate)) {`502 `if (llvm::isa<LoadOp>(op) && isReleaseOrAcqRel(atomic.getOrdering()))`false branchfalse branchtrue branch503 `return contractError("atomic load ordering must not be 'release' or "`504 `"'acq_rel'");`505 `if (llvm::isa<StoreOp>(op) && isAcquireOrAcqRel(atomic.getOrdering()))`false branchfalse branchtrue branch506 `return contractError("atomic store ordering must not be 'acquire' or "`507 `"'acq_rel'");`508 `}`509 `if (auto rmw = llvm::dyn_cast<AtomicRmwOp>(op))`510 `if (rmw.getContract().getAccess().getOrdering() ==`
`…/lib/Frontend/Lowering/LowerGraphMemoryPass.cpp`MS1V	525/841lines62.4% 208/400branches52.0%	557/841lines66.2%+32 229/400branches57.2%+21	+8 lines · +7 branchesseed 207 · 20 → 17 linesOpen PBT Review PR +9 lines · +8 branchesseed 3 · 19 → 19 linesOpen PBT Review PR +6 lines · +4 branchesseed 31 · 20 → 18 linesOpen PBT Review PR +11 lines · +8 branchesseed 40 · 19 → 18 linesOpen PBT Review PR +12 lines · +11 branchesseed 528 · 21 → 21 linesOpen PBT Review PR +14 lines · +11 branchesseed 1608 · 21 → 21 linesOpen PBT Review PR +10 lines · +8 branchesseed 1617 · 20 → 19 linesOpen PBT Review PR +4 lines · +3 branchesseed 2 · 15 → 15 linesOpen PBT Review PR +8 lines · +7 branchesseed 207 · 20 → 19 linesOpen PBT Review PR +14 lines · +11 branchesseed 2249 · 20 → 20 linesOpen PBT Review PR +9 lines · +7 branchesseed 2449 · 20 → 20 linesOpen PBT Review PR +8 lines · +7 branchesseed 2631 · 18 → 18 linesOpen PBT Review PR +6 lines · +4 branchesseed 31 · 20 → 18 linesOpen PBT Review PR +6 lines · +4 branchesseed 31 · 20 → 18 linesOpen PBT Review PR
32 newly covered lines · 21 newly covered branches 457 `case ::mlir::LLVM::AtomicOrdering::monotonic:`458 `return ::dataflow::AtomicOrdering::Monotonic;`459 `case ::mlir::LLVM::AtomicOrdering::acquire:`true branch460 `return ::dataflow::AtomicOrdering::Acquire;`461 `case ::mlir::LLVM::AtomicOrdering::release:`true branch462 `return ::dataflow::AtomicOrdering::Release;`463 `case ::mlir::LLVM::AtomicOrdering::acq_rel:`464 `return ::dataflow::AtomicOrdering::AcqRel;`⋮474`convertSyncScope(::mlir::MLIRContext context,`475 `std::optional<::llvm::StringRef> syncscope) {`476 `if (!syncscope \|\| syncscope->empty() \|\| syncscope == "system")`true branch477 `return ::dataflow::SyncScopeRefAttr::get(`478 `context, ::dataflow::SyncScopeKind::System);`⋮486`convertAtomicRmwKind(::mlir::LLVM::AtomicBinOp kind) {`487 `switch (kind) {`488 `case ::mlir::LLVM::AtomicBinOp::xchg:`true branch489 `return ::dataflow::AtomicRmwKind::Xchg;`490 `case ::mlir::LLVM::AtomicBinOp::add:`false branch491 `return ::dataflow::AtomicRmwKind::Add;`492 `case ::mlir::LLVM::AtomicBinOp::sub:`true branch493 `return ::dataflow::AtomicRmwKind::Sub;`494 `case ::mlir::LLVM::AtomicBinOp::_and:`true branch495 `return ::dataflow::AtomicRmwKind::And;`496 `case ::mlir::LLVM::AtomicBinOp::nand:`497 `return ::dataflow::AtomicRmwKind::Nand;`498 `case ::mlir::LLVM::AtomicBinOp::_or:`true branch499 `return ::dataflow::AtomicRmwKind::Or;`500 `case ::mlir::LLVM::AtomicBinOp::_xor:`true branch501 `return ::dataflow::AtomicRmwKind::Xor;`502 `case ::mlir::LLVM::AtomicBinOp::max:`true branch503 `return ::dataflow::AtomicRmwKind::Max;`504 `case ::mlir::LLVM::AtomicBinOp::min:`true branch505 `return ::dataflow::AtomicRmwKind::Min;`506 `case ::mlir::LLVM::AtomicBinOp::umax:`true branch507 `return ::dataflow::AtomicRmwKind::UMax;`508 `case ::mlir::LLVM::AtomicBinOp::umin:`true branch509 `return ::dataflow::AtomicRmwKind::UMin;`510 `case ::mlir::LLVM::AtomicBinOp::fadd:`511 `return ::dataflow::AtomicRmwKind::FAdd;`⋮656 `auto lowered = ::dataflow::LoadOp::create(`657 `builder, loc, elemTy, builder.getNoneType(), mem, address, ctx.ctrl);`658 `if (load.getOrdering() == ::mlir::LLVM::AtomicOrdering::not_atomic) {`false branch659 `lowered.setContractAttr(::dataflow::PlainAccessContractAttr::get(`660 `ctx.graph.getContext(), load.getVolatile_()));`661 `} else if (auto contract = makeAtomicAccessContract(`true branch662 `load, ctx.graph.getContext(), elemTy)) {`663 `lowered.setContractAttr(contract);`664 `} else {`665 `lowered.erase();`666 `return false;`⋮672 `builder, loc, builder.getNoneType(), mem, address, store.getValue(),`673 `ctx.ctrl);`674 `if (store.getOrdering() == ::mlir::LLVM::AtomicOrdering::not_atomic) {`false branch675 `lowered.setContractAttr(::dataflow::PlainAccessContractAttr::get(`676 `ctx.graph.getContext(), store.getVolatile_()));`677 `} else if (auto contract = makeAtomicAccessContract(`true branch678 `store, ctx.graph.getContext(), store.getValue().getType())) {`679 `lowered.setContractAttr(contract);`680 `} else {`681 `lowered.erase();`682 `return false;`⋮733 `::llvm::SmallVector<::mlir::LLVM::GEPOp, 8> dead;`734 `graph.getBody().walk([&](::mlir::LLVM::GEPOp gep) {`735 `if (gep->use_empty())`true branch736 `dead.push_back(gep);`737 `});`738 `for (::mlir::LLVM::GEPOp gep : dead) {`true branch739 `gep.erase();`740 `changed = true;`741 `}`742 `}`743`}`⋮768 `::llvm::SmallVector<::mlir::LLVM::LoadOp, 4> loads;`769 `graph.getBody().walk([&](::mlir::LLVM::LoadOp load) {`770 `if (!load.getVolatile_() &&`false branch771 `load.getOrdering() == ::mlir::LLVM::AtomicOrdering::not_atomic)`false branch772 `loads.push_back(load);`773 `});`
`…/lib/Frontend/Lowering/GraphRegionAdmission.cpp`MS1V	58/110lines52.7% 29/92branches31.5%	58/110lines52.7%+0 30/92branches32.6%+1	+1 branchseed 0 · 29 → 27 linesOpen PBT Review PR +1 branchseed 0 · 29 → 27 linesOpen PBT Review PR
1 newly covered branch 112 `if (operation->getNumRegions() == 0 && isEffectFree &&`113 `(dataflow::isCanonicalDataflowActor(operation) \|\|`114 `isGraphMemoryAddressLeaf(operation)))`true branch115 `return GraphLeafLowering::Movable;`116 `if (llvm::isa<mlir::memref::AssumeAlignmentOp,`
`…/lib/Frontend/Lowering/GraphRegionLowering.cpp`MS1V	1416/1626lines87.1% 532/680branches78.2%	1431/1626lines88.0%+15 539/680branches79.3%+7	+15 lines · +7 branchesseed 0 · 29 → 27 linesOpen PBT Review PR +15 lines · +7 branchesseed 0 · 29 → 27 linesOpen PBT Review PR
15 newly covered lines · 7 newly covered branches 593 `if (!def)`594 `return value;`595 `if (::llvm::isa<::mlir::memref::AllocOp, ::mlir::memref::AllocaOp,`false branch596 `::mlir::memref::GetGlobalOp>(def))`597 `return value;`598 `if (auto view = ::llvm::dyn_cast<::mlir::ViewLikeOpInterface>(def)) {`true branch599 `value = view.getViewSource();`600 `continue;`601 `}`602 `return std::nullopt;`603 `}`604 `return std::nullopt;`605 `}`⋮611 `::llvm::DenseSet<::mlir::Value> visited;`612 `while (value && visited.insert(value).second) {`613 `if (auto argument = ::llvm::dyn_cast<::mlir::BlockArgument>(value)) {`false branch614 `if (argument.getOwner() != &entry \|\| argument.getArgNumber() == 0)`615 `return true;`⋮618 `}`619620 `::mlir::Operation *def = value.getDefiningOp();`621 `if (!def)`false branch622 `return true;`623 `if (::llvm::isa<::mlir::memref::AllocOp, ::mlir::memref::AllocaOp,`false branchtrue branch624 `::mlir::memref::GetGlobalOp, ::mlir::LLVM::AddressOfOp>(`625 `def))`626 `return true;`627 `if (auto view = ::llvm::dyn_cast<::mlir::ViewLikeOpInterface>(def)) {`true branch628 `value = view.getViewSource();`629 `continue;`630 `}`631 `if (auto gep = ::llvm::dyn_cast<::mlir::LLVM::GEPOp>(def)) {`632 `value = gep.getBase();`
`…/lib/Dataflow/IR/DataflowMemoryContracts.cpp`MS2V	198/371lines53.4% 98/218branches45.0%	205/371lines55.3%+7 99/218branches45.4%+1	1 generated input reaches this file; none minimized yetOpen PBT
7 newly covered lines · 1 newly covered branch 390 `aggregate = PlainAccessContractAttr::get(typedOp.getContext(),`391 `/is_volatile=/false);`392 `if (auto plain = llvm::dyn_cast<PlainAccessContractAttr>(aggregate))`false branch393 `return MemoryActorContract{`394 `aggregate, /atomic=/false, plain.getIsVolatile(),`395 `std::nullopt, std::nullopt, SyncScopeRefAttr()};`396 `auto access = llvm::cast<AtomicAccessContractAttr>(aggregate);`397 `return MemoryActorContract{aggregate,`398 `/atomic=/true,`399 `access.getIsVolatile(),`400 `access.getSourceAlignmentBytes(),`401 `access.getVectorGranularity(),`402 `access.getSyncScope()};`403 `})`404 `.Case<AtomicRmwOp>([](AtomicRmwOp typedOp) {`
`…/lib/Frontend/Lowering/GraphIndexLowering.cpp`MS2V	260/288lines90.3% 129/168branches76.8%	264/288lines91.7%+4 130/168branches77.4%+1	+4 lines · +1 branchseed 3 · 41 → 34 linesOpen PBT Review PR +4 lines · +1 branchseed 3 · 41 → 41 linesOpen PBT Review PR
4 newly covered lines · 1 newly covered branch 91 `.getResult();`92 `});`93 `if (auto mul = value.getDefiningOp<::mlir::arith::MulIOp>())`true branch94 `return materializeBinary(mul, [&](::mlir::Value lhs, ::mlir::Value rhs) {`95 `return ::mlir::arith::MulIOp::create(builder, mul.getLoc(), lhs, rhs)`96 `.getResult();`97 `});`98 `if (auto shl = value.getDefiningOp<::mlir::arith::ShLIOp>())`99 `return materializeBinary(shl, [&](::mlir::Value lhs, ::mlir::Value rhs) {`

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Files without added coverage and unmeasured PBTs

Source file	Baseline coverage	Baseline + input	Contributing input
`…/loom/include/Common/Artifact.h`MS0V	13/37lines35.1% 3/18branches16.7%	13/37lines35.1%+0 3/18branches16.7%+0	Open PBT
`…/include/Dataflow/IR/DataflowActorSemantics.h`MS0V	9/160lines5.6% 1/60branches1.7%	9/160lines5.6%+0 1/60branches1.7%+0	Open PBT
`…/loom/lib/Common/IndexWidth.cpp`MS0V	63/84lines75.0% 28/42branches66.7%	63/84lines75.0%+0 28/42branches66.7%+0	Open PBT
`…/lib/Dataflow/IR/DataflowActorSemantics.cpp`MS0V	1089/1621lines67.2% 747/1330branches56.2%	1089/1621lines67.2%+0 747/1330branches56.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowChannelOps.cpp`MS0V	59/88lines67.0% 13/38branches34.2%	59/88lines67.0%+0 13/38branches34.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowDialect.cpp`MS0V	22/32lines68.8% 4/10branches40.0%	22/32lines68.8%+0 4/10branches40.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowFunctionLikeOps.cpp`MS0V	693/1097lines63.2% 264/592branches44.6%	693/1097lines63.2%+0 264/592branches44.6%+0	Open PBT
`…/lib/Dataflow/IR/DataflowOps.cpp`MS0V	270/410lines65.9% 103/228branches45.2%	270/410lines65.9%+0 103/228branches45.2%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchema.cpp`MS0V	274/716lines38.3% 127/350branches36.3%	274/716lines38.3%+0 127/350branches36.3%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaCodecInternal.h`MS0V	28/120lines23.3% 4/44branches9.1%	28/120lines23.3%+0 4/44branches9.1%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaTypeCodec.cpp`MS0V	85/516lines16.5% 55/374branches14.7%	85/516lines16.5%+0 55/374branches14.7%+0	Open PBT
`…/lib/Dataflow/Transforms/DataflowRewritePass.cpp`MS0V	338/559lines60.5% 172/340branches50.6%	338/559lines60.5%+0 172/340branches50.6%+0	Open PBT
`…/lib/Frontend/Lowering/ExpandGraphMemrefCopyPass.cpp`MS0V	79/90lines87.8% 20/22branches90.9%	79/90lines87.8%+0 20/22branches90.9%+0	Open PBT
`…/lib/Frontend/Lowering/GraphIndexLowering.cpp`MS0V	260/288lines90.3% 129/168branches76.8%	260/288lines90.3%+0 129/168branches76.8%+0	Open PBT
`…/lib/Frontend/Lowering/GraphParallelLowering.cpp`MS0V	651/1243lines52.4% 284/786branches36.1%	651/1243lines52.4%+0 284/786branches36.1%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionAdmission.cpp`MS0V	58/110lines52.7% 29/92branches31.5%	58/110lines52.7%+0 29/92branches31.5%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionLowering.cpp`MS0V	1416/1626lines87.1% 532/680branches78.2%	1416/1626lines87.1%+0 532/680branches78.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.cpp`MS0V	934/1072lines87.1% 299/432branches69.2%	934/1072lines87.1%+0 299/432branches69.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.h`MS0V	4/4lines100.0% 4/4branches100.0%	4/4lines100.0%+0 4/4branches100.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForToGraphPass.cpp`MS0V	1033/1240lines83.3% 374/540branches69.3%	1033/1240lines83.3%+0 374/540branches69.3%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForallToThreadPass.cpp`MS0V	30/34lines88.2% 2/4branches50.0%	30/34lines88.2%+0 2/4branches50.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphConstantsPass.cpp`MS0V	80/83lines96.4% 18/24branches75.0%	80/83lines96.4%+0 18/24branches75.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphMemoryPass.cpp`MS0V	525/841lines62.4% 208/400branches52.0%	525/841lines62.4%+0 208/400branches52.0%+0	Open PBT
`…/lib/Frontend/Lowering/Pipeline.cpp`MS0V	18/21lines85.7% branchesnot measured	18/21lines85.7%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/DeduplicateSCFWhileStatePass.cpp`MS0V	13/135lines9.6% 0/60branches0.0%	13/135lines9.6%+0 0/60branches0.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMArithToArithPass.cpp`MS0V	300/319lines94.0% 94/116branches81.0%	300/319lines94.0%+0 94/116branches81.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMCfToCfPass.cpp`MS0V	77/80lines96.2% 8/8branches100.0%	77/80lines96.2%+0 8/8branches100.0%+0	Open PBT
`…/lib/Frontend/Raising/LiftCFToSCFPass.cpp`MS0V	616/694lines88.8% 293/386branches75.9%	616/694lines88.8%+0 293/386branches75.9%+0	Open PBT
`…/lib/Frontend/Raising/MaterializeFMulAddPass.cpp`MS0V	70/106lines66.0% 11/26branches42.3%	70/106lines66.0%+0 11/26branches42.3%+0	Open PBT
`…/lib/Frontend/Raising/NormalizeLiftedSCFExitPass.cpp`MS0V	232/250lines92.8% 120/182branches65.9%	232/250lines92.8%+0 120/182branches65.9%+0	Open PBT
`…/lib/Frontend/Raising/Pipeline.cpp`MS0V	10/19lines52.6% branchesnot measured	10/19lines52.6%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/SCFForToForallPass.cpp`MS0V	494/738lines66.9% 241/458branches52.6%	494/738lines66.9%+0 241/458branches52.6%+0	Open PBT
`…/lib/Frontend/Raising/SCFWhileToForPass.cpp`MS0V	164/176lines93.2% 70/94branches74.5%	164/176lines93.2%+0 70/94branches74.5%+0	Open PBT
`…/loom/tools/loom-raise-opt/loom-raise-opt.cpp`MS0V	12/12lines100.0% branchesnot measured	12/12lines100.0%+0 branchesnot measured	Open PBT
`…/loom/include/Common/Artifact.h`MS1V	13/37lines35.1% 3/18branches16.7%	13/37lines35.1%+0 3/18branches16.7%+0	Open PBT
`…/include/Dataflow/IR/DataflowActorSemantics.h`MS1V	9/160lines5.6% 1/60branches1.7%	9/160lines5.6%+0 1/60branches1.7%+0	Open PBT
`…/include/Frontend/Lowering/StreamLoopAttrs.h`MS1V	31/41lines75.6% 10/14branches71.4%	31/41lines75.6%+0 10/14branches71.4%+0	Open PBT
`…/loom/lib/Common/IndexWidth.cpp`MS1V	63/84lines75.0% 28/42branches66.7%	63/84lines75.0%+0 28/42branches66.7%+0	Open PBT
`…/lib/Dataflow/IR/DataflowChannelOps.cpp`MS1V	59/88lines67.0% 13/38branches34.2%	59/88lines67.0%+0 13/38branches34.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowDialect.cpp`MS1V	22/32lines68.8% 4/10branches40.0%	22/32lines68.8%+0 4/10branches40.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowFunctionLikeOps.cpp`MS1V	693/1097lines63.2% 264/592branches44.6%	693/1097lines63.2%+0 264/592branches44.6%+0	Open PBT
`…/lib/Dataflow/IR/DataflowMemoryContracts.cpp`MS1V	198/371lines53.4% 98/218branches45.0%	198/371lines53.4%+0 98/218branches45.0%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchema.cpp`MS1V	274/716lines38.3% 127/350branches36.3%	274/716lines38.3%+0 127/350branches36.3%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaCodecInternal.h`MS1V	28/120lines23.3% 4/44branches9.1%	28/120lines23.3%+0 4/44branches9.1%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaTypeCodec.cpp`MS1V	85/516lines16.5% 55/374branches14.7%	85/516lines16.5%+0 55/374branches14.7%+0	Open PBT
`…/lib/Dataflow/Transforms/DataflowRewritePass.cpp`MS1V	338/559lines60.5% 172/340branches50.6%	338/559lines60.5%+0 172/340branches50.6%+0	Open PBT
`…/lib/Frontend/Lowering/ExactMemRefLayout.cpp`MS1V	61/143lines42.7% 26/80branches32.5%	61/143lines42.7%+0 26/80branches32.5%+0	Open PBT
`…/lib/Frontend/Lowering/ExpandGraphMemrefCopyPass.cpp`MS1V	79/90lines87.8% 20/22branches90.9%	79/90lines87.8%+0 20/22branches90.9%+0	Open PBT
`…/lib/Frontend/Lowering/GraphIndexLowering.cpp`MS1V	260/288lines90.3% 129/168branches76.8%	260/288lines90.3%+0 129/168branches76.8%+0	Open PBT
`…/lib/Frontend/Lowering/GraphParallelLowering.cpp`MS1V	651/1243lines52.4% 284/786branches36.1%	651/1243lines52.4%+0 284/786branches36.1%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionAdmission.cpp`MS1V	58/110lines52.7% 29/92branches31.5%	58/110lines52.7%+0 29/92branches31.5%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.cpp`MS1V	934/1072lines87.1% 299/432branches69.2%	934/1072lines87.1%+0 299/432branches69.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.h`MS1V	4/4lines100.0% 4/4branches100.0%	4/4lines100.0%+0 4/4branches100.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForToGraphPass.cpp`MS1V	1033/1240lines83.3% 374/540branches69.3%	1033/1240lines83.3%+0 374/540branches69.3%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForallToThreadPass.cpp`MS1V	30/34lines88.2% 2/4branches50.0%	30/34lines88.2%+0 2/4branches50.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphConstantsPass.cpp`MS1V	80/83lines96.4% 18/24branches75.0%	80/83lines96.4%+0 18/24branches75.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphMemoryPass.cpp`MS1V	525/841lines62.4% 208/400branches52.0%	525/841lines62.4%+0 208/400branches52.0%+0	Open PBT
`…/lib/Frontend/Lowering/Pipeline.cpp`MS1V	18/21lines85.7% branchesnot measured	18/21lines85.7%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/DeduplicateSCFWhileStatePass.cpp`MS1V	13/135lines9.6% 0/60branches0.0%	13/135lines9.6%+0 0/60branches0.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMArithToArithPass.cpp`MS1V	300/319lines94.0% 94/116branches81.0%	300/319lines94.0%+0 94/116branches81.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMCfToCfPass.cpp`MS1V	77/80lines96.2% 8/8branches100.0%	77/80lines96.2%+0 8/8branches100.0%+0	Open PBT
`…/lib/Frontend/Raising/LiftCFToSCFPass.cpp`MS1V	616/694lines88.8% 293/386branches75.9%	616/694lines88.8%+0 293/386branches75.9%+0	Open PBT
`…/lib/Frontend/Raising/MaterializeFMulAddPass.cpp`MS1V	70/106lines66.0% 11/26branches42.3%	70/106lines66.0%+0 11/26branches42.3%+0	Open PBT
`…/lib/Frontend/Raising/NormalizeLiftedSCFExitPass.cpp`MS1V	232/250lines92.8% 120/182branches65.9%	232/250lines92.8%+0 120/182branches65.9%+0	Open PBT
`…/lib/Frontend/Raising/Pipeline.cpp`MS1V	10/19lines52.6% branchesnot measured	10/19lines52.6%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/SCFForToForallPass.cpp`MS1V	494/738lines66.9% 241/458branches52.6%	494/738lines66.9%+0 241/458branches52.6%+0	Open PBT
`…/lib/Frontend/Raising/SCFWhileToForPass.cpp`MS1V	164/176lines93.2% 70/94branches74.5%	164/176lines93.2%+0 70/94branches74.5%+0	Open PBT
`…/loom/tools/loom-raise-opt/loom-raise-opt.cpp`MS1V	12/12lines100.0% branchesnot measured	12/12lines100.0%+0 branchesnot measured	Open PBT
`…/loom/include/Common/Artifact.h`MS1V	13/37lines35.1% 3/18branches16.7%	13/37lines35.1%+0 3/18branches16.7%+0	Open PBT
`…/include/Dataflow/IR/DataflowActorSemantics.h`MS1V	9/160lines5.6% 1/60branches1.7%	9/160lines5.6%+0 1/60branches1.7%+0	Open PBT
`…/include/Frontend/Lowering/StreamLoopAttrs.h`MS1V	31/41lines75.6% 10/14branches71.4%	31/41lines75.6%+0 10/14branches71.4%+0	Open PBT
`…/loom/lib/Common/IndexWidth.cpp`MS1V	63/84lines75.0% 28/42branches66.7%	63/84lines75.0%+0 28/42branches66.7%+0	Open PBT
`…/loom/lib/Common/PointerLayout.cpp`MS1V	36/58lines62.1% 16/32branches50.0%	36/58lines62.1%+0 16/32branches50.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowActorSemantics.cpp`MS1V	1089/1621lines67.2% 747/1330branches56.2%	1089/1621lines67.2%+0 747/1330branches56.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowChannelOps.cpp`MS1V	59/88lines67.0% 13/38branches34.2%	59/88lines67.0%+0 13/38branches34.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowDialect.cpp`MS1V	22/32lines68.8% 4/10branches40.0%	22/32lines68.8%+0 4/10branches40.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowFunctionLikeOps.cpp`MS1V	693/1097lines63.2% 264/592branches44.6%	693/1097lines63.2%+0 264/592branches44.6%+0	Open PBT
`…/lib/Dataflow/IR/DataflowOps.cpp`MS1V	270/410lines65.9% 103/228branches45.2%	270/410lines65.9%+0 103/228branches45.2%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchema.cpp`MS1V	274/716lines38.3% 127/350branches36.3%	274/716lines38.3%+0 127/350branches36.3%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaCodecInternal.h`MS1V	28/120lines23.3% 4/44branches9.1%	28/120lines23.3%+0 4/44branches9.1%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaTypeCodec.cpp`MS1V	85/516lines16.5% 55/374branches14.7%	85/516lines16.5%+0 55/374branches14.7%+0	Open PBT
`…/lib/Dataflow/Transforms/DataflowRewritePass.cpp`MS1V	338/559lines60.5% 172/340branches50.6%	338/559lines60.5%+0 172/340branches50.6%+0	Open PBT
`…/lib/Frontend/Lowering/ExpandGraphMemrefCopyPass.cpp`MS1V	79/90lines87.8% 20/22branches90.9%	79/90lines87.8%+0 20/22branches90.9%+0	Open PBT
`…/lib/Frontend/Lowering/GraphIndexLowering.cpp`MS1V	260/288lines90.3% 129/168branches76.8%	260/288lines90.3%+0 129/168branches76.8%+0	Open PBT
`…/lib/Frontend/Lowering/GraphMemoryAddressing.cpp`MS1V	189/557lines33.9% 83/442branches18.8%	189/557lines33.9%+0 83/442branches18.8%+0	Open PBT
`…/lib/Frontend/Lowering/GraphParallelLowering.cpp`MS1V	651/1243lines52.4% 284/786branches36.1%	651/1243lines52.4%+0 284/786branches36.1%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionAdmission.cpp`MS1V	58/110lines52.7% 29/92branches31.5%	58/110lines52.7%+0 29/92branches31.5%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionLowering.cpp`MS1V	1416/1626lines87.1% 532/680branches78.2%	1416/1626lines87.1%+0 532/680branches78.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.cpp`MS1V	934/1072lines87.1% 299/432branches69.2%	934/1072lines87.1%+0 299/432branches69.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.h`MS1V	4/4lines100.0% 4/4branches100.0%	4/4lines100.0%+0 4/4branches100.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForToGraphPass.cpp`MS1V	1033/1240lines83.3% 374/540branches69.3%	1033/1240lines83.3%+0 374/540branches69.3%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForallToThreadPass.cpp`MS1V	30/34lines88.2% 2/4branches50.0%	30/34lines88.2%+0 2/4branches50.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphConstantsPass.cpp`MS1V	80/83lines96.4% 18/24branches75.0%	80/83lines96.4%+0 18/24branches75.0%+0	Open PBT
`…/lib/Frontend/Lowering/Pipeline.cpp`MS1V	18/21lines85.7% branchesnot measured	18/21lines85.7%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/DeduplicateSCFWhileStatePass.cpp`MS1V	13/135lines9.6% 0/60branches0.0%	13/135lines9.6%+0 0/60branches0.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMArithToArithPass.cpp`MS1V	300/319lines94.0% 94/116branches81.0%	300/319lines94.0%+0 94/116branches81.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMCfToCfPass.cpp`MS1V	77/80lines96.2% 8/8branches100.0%	77/80lines96.2%+0 8/8branches100.0%+0	Open PBT
`…/lib/Frontend/Raising/LiftCFToSCFPass.cpp`MS1V	616/694lines88.8% 293/386branches75.9%	616/694lines88.8%+0 293/386branches75.9%+0	Open PBT
`…/lib/Frontend/Raising/MaterializeFMulAddPass.cpp`MS1V	70/106lines66.0% 11/26branches42.3%	70/106lines66.0%+0 11/26branches42.3%+0	Open PBT
`…/lib/Frontend/Raising/NormalizeLiftedSCFExitPass.cpp`MS1V	232/250lines92.8% 120/182branches65.9%	232/250lines92.8%+0 120/182branches65.9%+0	Open PBT
`…/lib/Frontend/Raising/Pipeline.cpp`MS1V	10/19lines52.6% branchesnot measured	10/19lines52.6%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/SCFForToForallPass.cpp`MS1V	494/738lines66.9% 241/458branches52.6%	494/738lines66.9%+0 241/458branches52.6%+0	Open PBT
`…/lib/Frontend/Raising/SCFWhileToForPass.cpp`MS1V	164/176lines93.2% 70/94branches74.5%	164/176lines93.2%+0 70/94branches74.5%+0	Open PBT
`…/loom/tools/loom-raise-opt/loom-raise-opt.cpp`MS1V	12/12lines100.0% branchesnot measured	12/12lines100.0%+0 branchesnot measured	Open PBT
`…/loom/include/Common/Artifact.h`MS1V	13/37lines35.1% 3/18branches16.7%	13/37lines35.1%+0 3/18branches16.7%+0	Open PBT
`…/include/Frontend/Lowering/StreamLoopAttrs.h`MS1V	31/41lines75.6% 10/14branches71.4%	31/41lines75.6%+0 10/14branches71.4%+0	Open PBT
`…/loom/lib/Common/IndexWidth.cpp`MS1V	63/84lines75.0% 28/42branches66.7%	63/84lines75.0%+0 28/42branches66.7%+0	Open PBT
`…/lib/Dataflow/IR/DataflowActorSemantics.cpp`MS1V	1089/1621lines67.2% 747/1330branches56.2%	1089/1621lines67.2%+0 747/1330branches56.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowChannelOps.cpp`MS1V	59/88lines67.0% 13/38branches34.2%	59/88lines67.0%+0 13/38branches34.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowDialect.cpp`MS1V	22/32lines68.8% 4/10branches40.0%	22/32lines68.8%+0 4/10branches40.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowFunctionLikeOps.cpp`MS1V	693/1097lines63.2% 264/592branches44.6%	693/1097lines63.2%+0 264/592branches44.6%+0	Open PBT
`…/lib/Dataflow/IR/DataflowMemoryContracts.cpp`MS1V	198/371lines53.4% 98/218branches45.0%	198/371lines53.4%+0 98/218branches45.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowOps.cpp`MS1V	270/410lines65.9% 103/228branches45.2%	270/410lines65.9%+0 103/228branches45.2%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchema.cpp`MS1V	274/716lines38.3% 127/350branches36.3%	274/716lines38.3%+0 127/350branches36.3%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaCodecInternal.h`MS1V	28/120lines23.3% 4/44branches9.1%	28/120lines23.3%+0 4/44branches9.1%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaTypeCodec.cpp`MS1V	85/516lines16.5% 55/374branches14.7%	85/516lines16.5%+0 55/374branches14.7%+0	Open PBT
`…/lib/Dataflow/Transforms/DataflowRewritePass.cpp`MS1V	338/559lines60.5% 172/340branches50.6%	338/559lines60.5%+0 172/340branches50.6%+0	Open PBT
`…/lib/Frontend/Lowering/ExactMemRefLayout.cpp`MS1V	61/143lines42.7% 26/80branches32.5%	61/143lines42.7%+0 26/80branches32.5%+0	Open PBT
`…/lib/Frontend/Lowering/ExpandGraphMemrefCopyPass.cpp`MS1V	79/90lines87.8% 20/22branches90.9%	79/90lines87.8%+0 20/22branches90.9%+0	Open PBT
`…/lib/Frontend/Lowering/GraphIndexLowering.cpp`MS1V	260/288lines90.3% 129/168branches76.8%	260/288lines90.3%+0 129/168branches76.8%+0	Open PBT
`…/lib/Frontend/Lowering/GraphParallelLowering.cpp`MS1V	651/1243lines52.4% 284/786branches36.1%	651/1243lines52.4%+0 284/786branches36.1%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.cpp`MS1V	934/1072lines87.1% 299/432branches69.2%	934/1072lines87.1%+0 299/432branches69.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.h`MS1V	4/4lines100.0% 4/4branches100.0%	4/4lines100.0%+0 4/4branches100.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForToGraphPass.cpp`MS1V	1033/1240lines83.3% 374/540branches69.3%	1033/1240lines83.3%+0 374/540branches69.3%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForallToThreadPass.cpp`MS1V	30/34lines88.2% 2/4branches50.0%	30/34lines88.2%+0 2/4branches50.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphConstantsPass.cpp`MS1V	80/83lines96.4% 18/24branches75.0%	80/83lines96.4%+0 18/24branches75.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphMemoryPass.cpp`MS1V	525/841lines62.4% 208/400branches52.0%	525/841lines62.4%+0 208/400branches52.0%+0	Open PBT
`…/lib/Frontend/Lowering/Pipeline.cpp`MS1V	18/21lines85.7% branchesnot measured	18/21lines85.7%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Lowering/RankedMemRefLowering.cpp`MS1V	60/133lines45.1% 27/94branches28.7%	60/133lines45.1%+0 27/94branches28.7%+0	Open PBT
`…/lib/Frontend/Raising/DeduplicateSCFWhileStatePass.cpp`MS1V	13/135lines9.6% 0/60branches0.0%	13/135lines9.6%+0 0/60branches0.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMArithToArithPass.cpp`MS1V	300/319lines94.0% 94/116branches81.0%	300/319lines94.0%+0 94/116branches81.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMCfToCfPass.cpp`MS1V	77/80lines96.2% 8/8branches100.0%	77/80lines96.2%+0 8/8branches100.0%+0	Open PBT
`…/lib/Frontend/Raising/LiftCFToSCFPass.cpp`MS1V	616/694lines88.8% 293/386branches75.9%	616/694lines88.8%+0 293/386branches75.9%+0	Open PBT
`…/lib/Frontend/Raising/MaterializeFMulAddPass.cpp`MS1V	70/106lines66.0% 11/26branches42.3%	70/106lines66.0%+0 11/26branches42.3%+0	Open PBT
`…/lib/Frontend/Raising/NormalizeLiftedSCFExitPass.cpp`MS1V	232/250lines92.8% 120/182branches65.9%	232/250lines92.8%+0 120/182branches65.9%+0	Open PBT
`…/lib/Frontend/Raising/Pipeline.cpp`MS1V	10/19lines52.6% branchesnot measured	10/19lines52.6%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/SCFForToForallPass.cpp`MS1V	494/738lines66.9% 241/458branches52.6%	494/738lines66.9%+0 241/458branches52.6%+0	Open PBT
`…/lib/Frontend/Raising/SCFWhileToForPass.cpp`MS1V	164/176lines93.2% 70/94branches74.5%	164/176lines93.2%+0 70/94branches74.5%+0	Open PBT
`…/loom/tools/loom-raise-opt/loom-raise-opt.cpp`MS1V	12/12lines100.0% branchesnot measured	12/12lines100.0%+0 branchesnot measured	Open PBT
`…/loom/include/Common/Artifact.h`MS2V	13/37lines35.1% 3/18branches16.7%	13/37lines35.1%+0 3/18branches16.7%+0	Open PBT
`…/include/Frontend/Lowering/StreamLoopAttrs.h`MS2V	31/41lines75.6% 10/14branches71.4%	31/41lines75.6%+0 10/14branches71.4%+0	Open PBT
`…/loom/lib/Common/IndexWidth.cpp`MS2V	63/84lines75.0% 28/42branches66.7%	63/84lines75.0%+0 28/42branches66.7%+0	Open PBT
`…/lib/Dataflow/IR/DataflowActorSemantics.cpp`MS2V	1089/1621lines67.2% 747/1330branches56.2%	1089/1621lines67.2%+0 747/1330branches56.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowChannelOps.cpp`MS2V	59/88lines67.0% 13/38branches34.2%	59/88lines67.0%+0 13/38branches34.2%+0	Open PBT
`…/lib/Dataflow/IR/DataflowDialect.cpp`MS2V	22/32lines68.8% 4/10branches40.0%	22/32lines68.8%+0 4/10branches40.0%+0	Open PBT
`…/lib/Dataflow/IR/DataflowFunctionLikeOps.cpp`MS2V	693/1097lines63.2% 264/592branches44.6%	693/1097lines63.2%+0 264/592branches44.6%+0	Open PBT
`…/lib/Dataflow/IR/DataflowOps.cpp`MS2V	270/410lines65.9% 103/228branches45.2%	270/410lines65.9%+0 103/228branches45.2%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchema.cpp`MS2V	274/716lines38.3% 127/350branches36.3%	274/716lines38.3%+0 127/350branches36.3%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaCodecInternal.h`MS2V	28/120lines23.3% 4/44branches9.1%	28/120lines23.3%+0 4/44branches9.1%+0	Open PBT
`…/lib/Dataflow/IR/OperationSchemaTypeCodec.cpp`MS2V	85/516lines16.5% 55/374branches14.7%	85/516lines16.5%+0 55/374branches14.7%+0	Open PBT
`…/lib/Dataflow/Transforms/DataflowRewritePass.cpp`MS2V	338/559lines60.5% 172/340branches50.6%	338/559lines60.5%+0 172/340branches50.6%+0	Open PBT
`…/lib/Frontend/Lowering/ExactMemRefLayout.cpp`MS2V	61/143lines42.7% 26/80branches32.5%	61/143lines42.7%+0 26/80branches32.5%+0	Open PBT
`…/lib/Frontend/Lowering/ExpandGraphMemrefCopyPass.cpp`MS2V	79/90lines87.8% 20/22branches90.9%	79/90lines87.8%+0 20/22branches90.9%+0	Open PBT
`…/lib/Frontend/Lowering/GraphParallelLowering.cpp`MS2V	651/1243lines52.4% 284/786branches36.1%	651/1243lines52.4%+0 284/786branches36.1%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionAdmission.cpp`MS2V	58/110lines52.7% 29/92branches31.5%	58/110lines52.7%+0 29/92branches31.5%+0	Open PBT
`…/lib/Frontend/Lowering/GraphRegionLowering.cpp`MS2V	1416/1626lines87.1% 532/680branches78.2%	1416/1626lines87.1%+0 532/680branches78.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.cpp`MS2V	934/1072lines87.1% 299/432branches69.2%	934/1072lines87.1%+0 299/432branches69.2%+0	Open PBT
`…/lib/Frontend/Lowering/GraphStreamBoundaryLowering.h`MS2V	4/4lines100.0% 4/4branches100.0%	4/4lines100.0%+0 4/4branches100.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForToGraphPass.cpp`MS2V	1033/1240lines83.3% 374/540branches69.3%	1033/1240lines83.3%+0 374/540branches69.3%+0	Open PBT
`…/lib/Frontend/Lowering/LowerForallToThreadPass.cpp`MS2V	30/34lines88.2% 2/4branches50.0%	30/34lines88.2%+0 2/4branches50.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphConstantsPass.cpp`MS2V	80/83lines96.4% 18/24branches75.0%	80/83lines96.4%+0 18/24branches75.0%+0	Open PBT
`…/lib/Frontend/Lowering/LowerGraphMemoryPass.cpp`MS2V	525/841lines62.4% 208/400branches52.0%	525/841lines62.4%+0 208/400branches52.0%+0	Open PBT
`…/lib/Frontend/Lowering/Pipeline.cpp`MS2V	18/21lines85.7% branchesnot measured	18/21lines85.7%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Lowering/RankedMemRefLowering.cpp`MS2V	60/133lines45.1% 27/94branches28.7%	60/133lines45.1%+0 27/94branches28.7%+0	Open PBT
`…/lib/Frontend/Raising/DeduplicateSCFWhileStatePass.cpp`MS2V	13/135lines9.6% 0/60branches0.0%	13/135lines9.6%+0 0/60branches0.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMArithToArithPass.cpp`MS2V	300/319lines94.0% 94/116branches81.0%	300/319lines94.0%+0 94/116branches81.0%+0	Open PBT
`…/lib/Frontend/Raising/LLVMCfToCfPass.cpp`MS2V	77/80lines96.2% 8/8branches100.0%	77/80lines96.2%+0 8/8branches100.0%+0	Open PBT
`…/lib/Frontend/Raising/LiftCFToSCFPass.cpp`MS2V	616/694lines88.8% 293/386branches75.9%	616/694lines88.8%+0 293/386branches75.9%+0	Open PBT
`…/lib/Frontend/Raising/MaterializeFMulAddPass.cpp`MS2V	70/106lines66.0% 11/26branches42.3%	70/106lines66.0%+0 11/26branches42.3%+0	Open PBT
`…/lib/Frontend/Raising/NormalizeLiftedSCFExitPass.cpp`MS2V	232/250lines92.8% 120/182branches65.9%	232/250lines92.8%+0 120/182branches65.9%+0	Open PBT
`…/lib/Frontend/Raising/Pipeline.cpp`MS2V	10/19lines52.6% branchesnot measured	10/19lines52.6%+0 branchesnot measured	Open PBT
`…/lib/Frontend/Raising/SCFForToForallPass.cpp`MS2V	494/738lines66.9% 241/458branches52.6%	494/738lines66.9%+0 241/458branches52.6%+0	Open PBT
`…/lib/Frontend/Raising/SCFWhileToForPass.cpp`MS2V	164/176lines93.2% 70/94branches74.5%	164/176lines93.2%+0 70/94branches74.5%+0	Open PBT
`…/loom/tools/loom-raise-opt/loom-raise-opt.cpp`MS2V	12/12lines100.0% branchesnot measured	12/12lines100.0%+0 branchesnot measured	Open PBT
derived from the coverage profile Open PBT	not measured	not measured	no drafts yet

– inputs

docs/spec-compiler-part-3-mem.md · pinned revision 48615bc5925ef4b9db8b4550b5d4322933cf4b7b

Loom Compiler Part 3 Memory Frontier Lowering

This document is the memory-order source of truth for graph-local SCF to Dataflow lowering. The concrete owner is loom-lower-graph-memory; it normalizes supported memory leaves and recursively lowers structured graph regions in one traversal.^MS2V36 · MS2V3 linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V5 · MS2V linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V74 · MS1V7 linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V43 · MS1V4 linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V22 · MS1V2 linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V71 · MS0V7 linked-input-67 · linked input 67generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

The Dataflow operation contracts remain owned by the Dataflow specifications. This document defines only the compiler analysis state and the ordinary SSA event network produced from it.

The resulting canonical memory actors and their explicit ctrl and done network are canonical software semantics. Their operation contracts are owned by docs/spec-dataflow-memory-consistency.md and docs/spec-dataflow-vectorization.md. TechMapping, SpatialMapping, and SystemMapping may realize that network on Fabric resources, but they must not reconstruct missing memory order from source order, graph text order, traversal, or physical placement. The downstream realization boundary is specified by docs/spec-mapping-memory.md.

1. Scope

The lowering contract covers:

scalar and fixed-ranked vector forms of canonical dataflow.load and dataflow.store, including the masked contiguous and gather/scatter forms defined by docs/spec-dataflow-vectorization.md;
canonical atomic load/store, dataflow.atomic_rmw, dataflow.cmpxchg, dataflow.fence, and volatile access contracts defined by docs/spec-dataflow-memory-consistency.md;

normalized scalar memref.load and memref.store leaves over a canonical linear memory space;^MS2V312 · MS2V3 linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V11 · MS2V linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V710 · MS1V7 linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V49 · MS1V4 linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V28 · MS1V2 linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V77 · MS0V7 linked-input-202 · linked input 202generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

sequential composition;

arbitrary nesting of scf.if, source-sequential scf.for, and scf.while;^MS2V318 · MS2V3 linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V17 · MS2V linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V716 · MS1V7 linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V415 · MS1V4 linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V214 · MS1V2 linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V713 · MS0V7 linked-input-184 · linked input 184generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

basic graph-local alias-root partitions;
conservative unknown accesses;
value, execution, write-frontier, and read-frontier projection through the same structured selectors;

pre-mutation rejection of residual scf.parallel and scf.forall that reach a graph without an already materialized schedule boundary.^MS2V324 · MS2V3 linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V23 · MS2V linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V722 · MS1V7 linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V421 · MS1V4 linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V220 · MS1V2 linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V719 · MS0V7 linked-input-200 · linked input 200generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

The lowering does not select parallel width, ownership, serialization, unrolling, reduction order, or any other schedule policy. Those decisions must be made before graph-region lowering and normalized into supported structured input.^MS2V330 · MS2V3 linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V29 · MS2V linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V728 · MS1V7 linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V427 · MS1V4 linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V226 · MS1V2 linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V725 · MS0V7 linked-input-149 · linked input 149generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

2. One Recursive Owner

The compiler-local contract is:

lower_region(E_in, values_in, {W_in[p], R_in[p]}, SB_in)
  -> (E_out, values_out, {W_out[p], R_out[p]}, SB_out)

E is execution permission and structural completion. W and R are memory-order frontiers for alias partition p. They share the ordinary none SSA type but remain semantically distinct throughout lowering. SB is the path-sensitive analysis relation containing only sequenced-before obligations that remain observable after the selected Structured Program Candidate's legal transformations. It covers atomic/fence, volatile, release, and acquire requirements across alias partitions. It is not one serialized token or an IR object.

The contract is an implementation function, not an IR object. Canonical IR does not contain partition ids, dependence snapshots, compound-region objects, chain-scope attributes, memory tokens, sequenced-before records, or memory-specific join operations.

The recursive owner replaces the former split among reduction, invariant, control, and sync passes. No later pass reconstructs structured memory order or graph completion from a hidden effect scan.

3. Basic Alias Partitions

Partition identity is local to one dataflow.graph lowering run.

A canonical root is found by peeling an accepted side-effect-free memref view until reaching an explicit storage or boundary root. The finalized surface recognizes:

a graph memory input, whose root identity comes from its launch binding;
a dataflow.memory.service result at that binding, which preserves the root of its exact pointer operand while changing only the value-plane pointer into a memory-plane capability;
a fresh memref.alloc result, whose root is unique for each invocation;
a verified side-effect-free view that preserves the source root. The initial accepted set contains memref.cast; adding another view form requires one matching root, region, and simulator contract before admission.^MS0V731 · MS0V7 linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V232 · MS1V2 linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V433 · MS1V4 linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V734 · MS1V7 linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V35 · MS2V linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V336 · MS2V3 linked-input-68 · linked input 68generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

When graph publication can trace every captured memory capability to a known root, an exact service rooted at a unique thread argument mechanically inherits that argument's llvm.noalias fact. If a root is unknown, appears through more than one captured capability, or does not resolve to that argument, publication must omit the fact. The service result does not independently assert aliasing, and graph publication does not perform another alias analysis.^MS2V342 · MS2V3 linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V41 · MS2V linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V740 · MS1V7 linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V439 · MS1V4 linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V238 · MS1V2 linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V737 · MS0V7 linked-input-32 · linked input 32generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

Graph launch memory bindings require exact memref capability types. An LLVM pointer cannot bind a graph memref through a conversion, inferred base, or special address-space-zero rule. SCF optimization may first prove and materialize a rooted memref capability plus integer offset, or it may retain the pointer as a value consumed by a PointerAddressed memory actor together with an independently bound service capability. Neither path materializes a graph-body bridge. builtin.unrealized_conversion_cast is never a canonical root, view, actor, or boundary bridge.^MS2V348 · MS2V3 linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V47 · MS2V linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V746 · MS1V7 linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V445 · MS1V4 linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V244 · MS1V2 linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V743 · MS0V7 linked-input-80 · linked input 80generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

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The Canonical Dataflow finalizer assigns one LogicalMemoryRootRef to each static imported-memory formal role and canonical fresh-allocation definition. An imported graph memory argument does not create a competing root: its exact dataflow.graph.launch binding resolves through root-preserving views to the upstream static role. A fresh allocation result is the root-defining value. View operations remain typed structural relations and receive no root ID of their own.

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Persistent consumers use the closed forms owned by docs/spec-compiler-part-3-dfg.md: LogicalMemoryViewRef, LogicalMemoryRootOrViewRef, and MemoryExposureRef. This document does not redeclare their wire variants.

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The root-local inventory resolves every admitted static view to its unique root-preserving relation. Reusing one graph under different roots creates separate structural view references in those root inventories rather than a view entity. A memory exposure identifies one launch-contextual graph memory result. It describes a provided capability boundary, not a token producer or an addressed memory operation.

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This persistent reference identifies a static software role. Runtime object identity is derived separately: an import is bound through the exact launch and runtime memory registry, while a fresh allocation combines its static root reference with the graph invocation occurrence. Two imported roles may resolve to one runtime object through explicit alias topology without merging their static IDs. Partition identity below remains local analysis state and is not the persistent root catalog.

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A memory input binds an established external memref capability through an exact graph-launch type match. An LLVM pointer never satisfies a graph memory port. A first-class pointer value used by a PointerAddressed actor resolves through the runtime object registry to one object and byte offset independently of the service-capability binding.^MS2V354 · MS2V3 linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V53 · MS2V linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V752 · MS1V7 linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V451 · MS1V4 linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V250 · MS1V2 linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V749 · MS0V7 linked-input-59 · linked input 59generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

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Distinct graph memory inputs are conservatively may-alias unless explicit no-alias evidence distinguishes them. Distinct fresh allocations are independent roots. The analysis does not use address ranges, affine disjointness, bank identity, physical ports, or element-type compatibility to split a root.^MS2V360 · MS2V3 linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V59 · MS2V linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V758 · MS1V7 linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V457 · MS1V4 linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V256 · MS1V2 linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V755 · MS0V7 linked-input-126 · linked input 126generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

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memref.get_global, memref.alloca, globals, static pointer bases, and unrecognized capability producers are not canonical roots. A pre-final analysis may conservatively group an unresolved access while building an event network, but finalization rejects any such residual producer rather than granting it an external-memory authority.^MS2V366 · MS2V3 linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V65 · MS2V linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V764 · MS1V7 linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V463 · MS1V4 linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V262 · MS1V2 linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V761 · MS0V7 linked-input-50 · linked input 50generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

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A source-origin llvm.alloca accepted by the Structured PromoteOrderedBufferToChannel decision is not an exception to this rule. That decision must remove the complete proved allocation closure before D0; a residual allocation or pointer use remains non-canonical and is rejected.^MS2V372 · MS2V3 linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V71 · MS2V linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V770 · MS1V7 linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V469 · MS1V4 linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V268 · MS1V2 linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V767 · MS0V7 linked-input-170 · linked input 170generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

159

Access-to-partition membership is kept in a transient operation map before SCF operands are projected. Selector demuxing must not change alias identity. The map is discarded after explicit event edges are emitted.^MS2V378 · MS2V3 linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V77 · MS2V linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V776 · MS1V7 linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V475 · MS1V4 linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V274 · MS1V2 linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V773 · MS0V7 linked-input-195 · linked input 195generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

163

4. Canonical Frontier State

165

Each partition has exactly two alias-hazard analysis values:

167

(write_frontier[p], read_frontier[p])

171

write_frontier[p] covers the maximal write tail not superseded by a later causal write. read_frontier[p] covers that write frontier plus maximal reads not superseded by a later write. The invariant is:

175

write_frontier[p] <= read_frontier[p]

179

At graph entry, both components equal the leading graph start value for every partition. A region that does not touch p forwards both components without creating projection or recurrence actors.

183

Compiler join means an all-of causal frontier. It is materialized with ordinary dataflow.sync after deduplication and conservative transitive reduction. Mutually exclusive alternatives use dataflow.mux, never dataflow.sync.

188

Cross-partition sequenced-before requirements do not add another component to each alias partition. The implementation may use disposable all-effect, atomic/fence, volatile, and acquire frontier caches to compress SB, but the required relation is the authority. Cache shape, traversal order, and intermediate joins are not observable and are discarded after event edges are published.

195

5. Leaf Transfers

197

For a read covering partitions P(access):

199

ctrl = join(E, W[p] for p in P(access))
done = read.done
W[p] remains unchanged
R[p] = join(R[p], done)

206

For a write covering partitions P(access):

208

ctrl = join(E, R[p] for p in P(access))
done = write.done
W[p] = done
R[p] = done

215

These equations are the complete hazard authority:

217

RAW: a read waits for the current write frontier;
WAR: a write waits for all outstanding reads;
WAW: a write waits for the read frontier, which covers the prior write;
RAR: a read does not wait for prior reads.

222

Atomic load uses the read equation and atomic store uses the write equation. Atomic RMW and compare-exchange conservatively use the write equation because each firing may both read and write; a failed compare-exchange may retain the resulting causal edge without inventing a write. Fence has no alias-partition read or write effect.

228

In addition to alias hazards, lowering materializes the sequenced-before rules from the actor contracts:

atomic actors and fences in one logical source strand preserve their selected order;
volatile actors in one logical source strand preserve their relative order;
release actors and fences wait for prior memory-effect tails whose visibility they publish;
acquire actors and fences precede later constrained memory effects;
acq_rel and seq_cst apply both directions; and
atomic-volatile actors participate in both strand relations.^MS0V7n/a79 · MS0V7 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationstrace evidence 1000 samples / 664 classesopen PBT →

240

These ordinary event edges preserve local ordering only. Reads-from, modification order, synchronizes-with, and the global sequentially-consistent order remain dynamic consistency-domain state. Different dynamic thread instances are not joined by a compiler-created global frontier.

245

One vector addressed memory actor is one canonical firing. Its active lanes do not create independent frontier records or an implicit lane order. P(access) is the conservative union of alias partitions that any active lane may access. A dynamic mask or address vector cannot weaken that set merely because one observed execution disables a lane. A statically proven all-zero mask may be simplified by an ordinary semantics-preserving Dataflow rewrite; otherwise the firing retains its explicit ctrl and done obligations.^MS2V386 · MS2V3 linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V85 · MS2V linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V784 · MS1V7 linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V483 · MS1V4 linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V282 · MS1V2 linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V256.2%81 · MS1V2 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1000 samples / 10 classesopen PBT →^MS0V780 · MS0V7 linked-input-211 · linked input 211generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

253

The vector operation's owning semantic contract determines lane activity, inactive-load fill, duplicate-gather behavior, and rejection or explicit ordering of duplicate scatter addresses. This lowering only projects the whole firing through the same (W,R) equations as a scalar access. It does not define a second vector-memory ordering model.

259

For R0; R1; W2; R3 on one partition, R0 and R1 both receive the incoming write frontier. W2 receives an all-of of both read completions. R3 receives W2.done. A different root keeps its own incoming frontier and receives no cross-partition edge.

264

Memory completion does not become execution permission. A straight-line leaf does not replace E; its effects are represented only in W/R. This avoids reintroducing RAR order through a structural token. Structured children do produce a new E_out, and a parent continuation waits for that structural exit.

270

6. Selection

272

For scf.if, the condition drives all projections:

274

demux E_in into false and true execution lanes;
demux every captured non-memory value into matching lanes;
demux W_in[p] and R_in[p] for each partition touched by either branch;
project the required SB_in tails through the same branch selector;
recursively lower each branch;
mux results, execution, W, R, and path-sensitive SB tails with the same condition.

282

Memref bindings are static capabilities and are not demuxed. Address, data, selector, and event values are projected as ordinary streams.

285

A missing else region is an identity false path. Its execution lane and every touched incoming frontier component flow directly to the corresponding mux. No fake load, fake store, safe address, dummy done, or eager arith.select may stand in for an unexecuted memory access.

290

The same captured value may feed several uses within one branch; normal SSA multi-use provides token broadcast. A branch-local zero-operand constant is converted to dataflow.constant using that branch's execution permission.

294

7. Source-Sequential `scf.for`

296

dataflow.stream produces K valid induction values and a T^K F loop selector. Index bounds are cast to the configured integer index width before the stream and the induction value is cast back for source index uses.

300

The loop owns independent recurrence rings for:

302

execution permission;
every source iter_arg;
W[p] for each touched partition;
R[p] for each touched partition.

307

Required sequenced-before tails use the same condition-driven recurrence mechanics when they cross an iteration. This does not serialize unrelated plain accesses or create a persistent loop-order object.

311

Each ring uses dataflow.carry under the loop selector. A matching dataflow.demux sends true-lane values into the body and the false-lane value to loop exit. Captured non-memory values are replayed with dataflow.invariant and projected into body phase with dataflow.gate. Memref capabilities are not replayed.

317

The recursively lowered body supplies all recurrence feedback values. The execution feedback is the body's structural exit; memory feedback is the body's resulting frontier pair and any path-live sequenced-before tails. The rings are independent even when a write assigns the same done to both memory components.

323

For zero trip count, the stream emits only F. No body address or access fires. Every carry exposes its init value on the false lane, so source values, execution, W, R, and SB transfer through the loop unchanged.

327

No dependence is removed because a loop appears parallelizable. Source iteration order remains authoritative until an earlier transformation has materialized a different schedule with provenance.^MS2V91.9%87 · MS2V selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1000 samples / 236 classesopen PBT →

331

8. `scf.while`

333

For a while loop whose after region executes K times:

335

before executes K + 1 times;
after executes K times;
the before condition stream is T^K F.

339

Execution, source inits, touched W/R components, and path-live SB tails use condition-driven carry rings. Their outputs enter before directly, because before includes the final false condition check.

343

After recursively lowering before:

false-lane execution is E_out;
dataflow.gate projects before execution into after phase;
false-lane condition arguments become while results;
true-lane condition arguments become after block values;
false-lane W/R is the loop exit state;
true-lane W/R enters after;
false-lane SB tails leave the loop; and
true-lane SB tails enter after.^MS2V3100.0%88 · MS2V3 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1000 samples / 172 classesopen PBT →

354

After results feed the next before activation. A false condition consumes no dummy feedback.

357

The final false before effects are therefore visible at loop exit. A read in that final before activation updates R_out; a following write outside the loop must wait for it. For K = 0, before still executes once, after does not execute, and the first before effects remain in the outgoing frontier.

362

If the condition never becomes false, no execution exit, frontier exit, or while result is produced.

365

9. Nested Composition

367

Nesting uses only function composition of lower_region:

369

an inner while exit becomes the outer for body result and recurrence feedback;
an inner for is lowered entirely within the selected execution and frontier lanes of an outer if;
deeper combinations repeat the same rules without dedicated pairwise lowering paths.

376

The parent consumes only the child's execution, yielded values, frontier pair, and path-live sequenced-before tails. It does not reach into child leaves to reconstruct a tail.

380

10. Parallel Transfer Boundary

382

Residual scf.parallel or scf.forall is checked across every graph before the pass mutates any graph. Raw or unowned parallel input fails. A fixed finite parallel region is accepted only when its Structured Program Candidate owns a typed, verifier-proven P[] schedule and the recursive transfer can derive one complete frontier relation for that exact domain. The lowering must not trust the mere presence of string-named attributes as proof.^MS2V394 · MS2V3 linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V93 · MS2V linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V792 · MS1V7 linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V491 · MS1V4 linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V290 · MS1V2 linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V789 · MS0V7 linked-input-182 · linked input 182generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

389

Until the typed producer and verifier establish this provenance, the boundary fails closed. Forged, malformed, foreign-owner, or domain-mismatched provenance is invalid even when the residual SCF shape is otherwise supported. Part 3 consumes the selected schedule; it does not choose parallel width, serialization, ownership, or reduction order.^MS2V3100 · MS2V3 linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V99 · MS2V linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V798 · MS1V7 linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V497 · MS1V4 linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V296 · MS1V2 linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS0V795 · MS0V7 linked-input-102 · linked input 102generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →

395

The graph-region owner does not:

397

infer a width or ownership domain;
serialize the region;
unroll it;
choose reduction order;
use traversal order as a hidden schedule.

403

11. Graph Boundary

405

dataflow.graph.return is a structural graph-boundary declaration, not an implicit runtime return. Its operand segments are:

408

values(...) streams(...) memories(...) complete(...)

412

complete is mandatory, non-empty, variadic, unordered all-of, and contains only none values. The launch-facing done event is exactly:

415

launch.done = all_of(graph.return.complete)

419

There is no hidden effect scan, graph-quiescence test, or removed sync pass that can define completion independently.

422

A memory result in the memories segment is a MemoryExposureRef. Returning the capability does not issue a memory service operation and therefore creates no request, response, or completion leg. Mapping may bind the exposure to a provider boundary, but the actual service legs remain owned by the addressed memory actors that later use the capability.

428

After canonical publication, TechMapping may classify an explicit edge as realization-internal or external. SpatialMapping and SystemMapping may select the physical mechanisms that preserve it. No Mapping profile deletes, infers, or replaces the canonical load/store ctrl and done obligations. The Canonical Dataflow Program remains the memory-order source of truth.

434

After recursive lowering, this pass constructs the memory-owned retirement frontier from:

437

execution_out
read_frontier_out[p] for every live alias partition p
terminal observable sequenced-before tails
existing explicit non-start completion obligations

444

The candidate set is deduplicated and causally transitively reduced. A graph with no derived work and no value publication may retain %start. Once a derived execution or memory frontier exists, the provisional %start witness is removed. The reduced frontier is joined to one publication base. Each transportable scalar value is passed through a (none, T) -> (none, T) dataflow.sync with that base; the returned values use the typed outputs and the complete segment is the all-of of the none outputs. Pointer and memref capability payloads remain boundary bookkeeping whose establishment is covered by the structural and memory frontier rather than by a transport sync. With no scalar value outputs, the reduced none frontier is written directly to complete.

456

The frontier's causal closure covers final values, stream boundary close and commit obligations, memory capability establishment and promised visibility, all observable side effects, invocation-local state close/reset, and all non-detached async work. This pass contributes structural execution and final per-partition read frontiers; stream, exported-memory, and other async producers must contribute their explicit completion witnesses through the same segment. It never reconstructs them from operation order or effect metadata.

463

Memory exports preserve an imported root or view, or expose a fresh allocation root. Every export retains a memref result payload. Exports do not copy contents and do not add a memory token; completion only carries the promised visibility and retirement obligation.^MS1V799.6%101 · MS1V7 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1000 samples / 9 classesopen PBT →

468

12. Supported Failure Modes

470

The owner rejects before mutation when:

raw or unverifiably owned parallel SCF reaches a graph;
an effectful or unmodeled nested operation reaches a graph;
a residual LLVM load, store, atomicrmw, cmpxchg, fence, memcpy, memmove, or memset remains after normalization and therefore has no explicit completion event;
a source memory access has not been normalized to the canonical linear memory-space form required by its scalar or vector Dataflow actor;
structured control carries a memref result or memref loop state;
the graph entry lacks the leading none execution value.^MS0V7102 · MS0V7 linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2103 · MS1V2 linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4104 · MS1V4 linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7105 · MS1V7 linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V106 · MS2V linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3107 · MS2V3 linked-input-104 · linked input 104generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

482

LLVM memcpy, memmove, and memset intrinsics are expanded into their exact structured loop semantics before ownership selection. Supported LLVM load/store (including volatile and atomic contracts), atomicrmw, cmpxchg, and fence forms are then normalized before recursive region lowering, after^MS0V7108 · MS0V7 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2109 · MS1V2 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V427.4%110 · MS1V4 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1003 samples / 37 classesopen PBT →^MS1V4111 · MS1V4 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7112 · MS1V7 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V113 · MS2V linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3114 · MS2V3 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

486

which the same frontier rules apply. LLVM target-specific sync scopes without^MS0V7108 · MS0V7 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS0V7115 · MS0V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2109 · MS1V2 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V2116 · MS1V2 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V427.4%110 · MS1V4 selected-output · selected outputproperty — checked on every compiled pairSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedtrace evidence 1003 samples / 37 classesopen PBT →^MS1V4111 · MS1V4 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4117 · MS1V4 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7112 · MS1V7 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7118 · MS1V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V113 · MS2V linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V119 · MS2V linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3114 · MS2V3 linked-input-29 · linked input 29generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3120 · MS2V3 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

487

a compiler-target owner and atomic accesses without an explicit power-of-two source alignment fail closed. Every residual raw LLVM memory operation fails^MS0V7115 · MS0V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2116 · MS1V2 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4117 · MS1V4 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7118 · MS1V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V119 · MS2V linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3120 · MS2V3 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

489

closed. The finalized-graph gate also rejects residual^MS0V7121 · MS0V7 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS0V7115 · MS0V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2122 · MS1V2 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V2116 · MS1V2 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4123 · MS1V4 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4117 · MS1V4 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7124 · MS1V7 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7118 · MS1V7 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V125 · MS2V linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V119 · MS2V linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3126 · MS2V3 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3120 · MS2V3 linked-input-115 · linked input 115generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

490

memref.load/memref.store, memref.get_global, raw pointer arithmetic, pointer-bearing operations, builtin.unrealized_conversion_cast, and unknown memory-capability producers. An unsupported effectful operation inside a structured region must likewise fail closed instead of being hoisted.^MS0V7121 · MS0V7 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:b2259d118a5c5dd477532292 with its governing context; report any stage at1000 generated · 1000 paired97 potential violationsopen PBT →^MS1V2122 · MS1V2 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:fbc14afa5b8a77427b8b9322 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V4123 · MS1V4 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:25d0e7a02785d0c8ae044a98 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS1V7124 · MS1V7 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:280282c586f6f8051d51d7e3 with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V125 · MS2V linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:447d1981847b34fd70e40ebb with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →^MS2V3126 · MS2V3 linked-input-66 · linked input 66generator constraint — feeds the generated inputsSelected stage: loom-lower-graph-memory. Test exactly output obligation mlir-obligation:21c7df01d8d775342d1098ea with its governing context; report any stage at5000 generated · 5000 pairedopen PBT →

495

13. Non-Goals

497

This lowering does not define:

499

vector lane behavior, masks, gather/scatter address semantics, or duplicate scatter policy, which are owned by docs/spec-dataflow-vectorization.md;
range-sensitive or polyhedral alias partitioning;
cross-graph partition identity;
Fabric memory banks, ports, services, or contention;
runtime selection of graph stream or memory boundary bindings;
whole-graph causal-closure proof for arbitrary hand-authored frontiers;
parallel schedule selection.

508

Physical vector ports, byte enables, coalescing, banking, and memory-service selection belong to Fabric and Mapping. Those concerns must consume the explicit canonical event network or be owned by an earlier transformation. They must not rebuild memory order from source text order, simulator traversal, or physical placement.

514

TechMapping and physical memory realization are specified by docs/spec-mapping-artifact.md and docs/spec-mapping-memory.md; this compiler spec does not duplicate their records or search rules.

docs/spec-compiler-part-3-mem.md

Loom Compiler Part 3 Memory Frontier Lowering

1. Scope

2. One Recursive Owner

3. Basic Alias Partitions

4. Canonical Frontier State

5. Leaf Transfers

6. Selection

7. Source-Sequential scf.for

8. scf.while

9. Nested Composition

10. Parallel Transfer Boundary

11. Graph Boundary

12. Supported Failure Modes

13. Non-Goals

7. Source-Sequential `scf.for`

8. `scf.while`