{"entries":[{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"3-6","path":"docs/spec-compiler-part-3-mem.md","roles":["applicability"],"text":"This document is the memory-order source of truth for graph-local SCF to\nDataflow lowering. The concrete owner is `loom-lower-graph-memory`; it\nnormalizes supported memory leaves and recursively lowers structured graph\nregions in one traversal.","why":"Names loom-lower-graph-memory as the concrete owner of graph-local SCF to Dataflow memory lowering, fixing the pass under test and the graph-local scope of the sampled inputs."},{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"23-46","path":"docs/spec-compiler-part-3-mem.md","roles":["input_construction","input_well_formedness"],"text":"The lowering contract covers:\n\n* scalar and fixed-ranked vector forms of canonical `dataflow.load` and\n  `dataflow.store`, including the masked contiguous and gather/scatter forms\n  defined by `docs/spec-dataflow-vectorization.md`;\n* canonical atomic load/store, `dataflow.atomic_rmw`,\n  `dataflow.cmpxchg`, `dataflow.fence`, and volatile access contracts defined\n  by `docs/spec-dataflow-memory-consistency.md`;\n* normalized scalar `memref.load` and `memref.store` leaves over a canonical\n  linear memory space;\n* sequential composition;\n* arbitrary nesting of `scf.if`, source-sequential `scf.for`, and\n  `scf.while`;\n* basic graph-local alias-root partitions;\n* conservative unknown accesses;\n* value, execution, write-frontier, and read-frontier projection through the\n  same structured selectors;\n* pre-mutation rejection of residual `scf.parallel` and `scf.forall` that\n  reach a graph without an already materialized schedule boundary.\n\nThe lowering does not select parallel width, ownership, serialization,\nunrolling, reduction order, or any other schedule policy. Those decisions\nmust be made before graph-region lowering and normalized into supported\nstructured input.","why":"Defines the supported input surface the grammar samples: fixed-ranked vector dataflow.load/store including masked contiguous and gather/scatter forms, normalized scalar memref.load/store leaves over a canonical linear memory space, sequential composition, scf.if/scf.for nesting, and the exclusion of residual scf.parallel/scf.forall and of schedule-policy decisions."},{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"79-106","path":"docs/spec-compiler-part-3-mem.md","roles":["input_well_formedness"],"text":"A canonical root is found by peeling an accepted side-effect-free memref view\nuntil reaching an explicit storage or boundary root. The finalized surface\nrecognizes:\n\n* a graph memory input, whose root identity comes from its launch binding;\n* a `dataflow.memory.service` result at that binding, which preserves the root\n  of its exact pointer operand while changing only the value-plane pointer into\n  a memory-plane capability;\n* a fresh `memref.alloc` result, whose root is unique for each invocation;\n* a verified side-effect-free view that preserves the source root. The initial\n  accepted set contains `memref.cast`; adding another view form requires one\n  matching root, region, and simulator contract before admission.\n\nWhen graph publication can trace every captured memory capability to a known\nroot, an exact service rooted at a unique thread argument mechanically inherits\nthat argument's `llvm.noalias` fact. If a root is unknown, appears through more\nthan one captured capability, or does not resolve to that argument, publication\nmust omit the fact. The service result does not independently assert aliasing,\nand graph publication does not perform another alias analysis.\n\nGraph launch memory bindings require exact memref capability types. An LLVM\npointer cannot bind a graph memref through a conversion, inferred base, or\nspecial address-space-zero rule. SCF optimization may first prove and\nmaterialize a rooted memref capability plus integer offset, or it may retain\nthe pointer as a value consumed by a `PointerAddressed` memory actor together\nwith an independently bound service capability. Neither path materializes a\ngraph-body bridge. `builtin.unrealized_conversion_cast` is never a canonical\nroot, view, actor, or boundary bridge.","why":"Canonical roots and graph launch bindings: graph memref capability inputs are canonical roots with exact memref types, so the grammar binds every access to graph memref inputs and never to LLVM pointers, conversions, or bridges."},{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"136-161","path":"docs/spec-compiler-part-3-mem.md","roles":["input_construction","input_well_formedness"],"text":"A memory input binds an established external memref capability through an\nexact graph-launch type match. An LLVM pointer never satisfies a graph memory\nport. A first-class pointer value used by a `PointerAddressed` actor resolves\nthrough the runtime object registry to one object and byte offset independently\nof the service-capability binding.\n\nDistinct graph memory inputs are conservatively may-alias unless explicit\nno-alias evidence distinguishes them. Distinct fresh allocations are\nindependent roots. The analysis does not use address ranges, affine\ndisjointness, bank identity, physical ports, or element-type compatibility to\nsplit a root.\n\n`memref.get_global`, `memref.alloca`, globals, static pointer bases, and\nunrecognized capability producers are not canonical roots. A pre-final\nanalysis may conservatively group an unresolved access while building an event\nnetwork, but finalization rejects any such residual producer rather than\ngranting it an external-memory authority.\n\nA source-origin `llvm.alloca` accepted by the Structured\n`PromoteOrderedBufferToChannel` decision is not an exception to this rule. That\ndecision must remove the complete proved allocation closure before D0; a\nresidual allocation or pointer use remains non-canonical and is rejected.\n\nAccess-to-partition membership is kept in a transient operation map before\nSCF operands are projected. Selector demuxing must not change alias identity.\nThe map is discarded after explicit event edges are emitted.","why":"Distinct graph memory inputs are conservatively may-alias and memref.get_global/memref.alloca/global/static pointer bases are not canonical roots; justifies sampling two may-alias memref inputs and excluding non-root producers."},{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"245-251","path":"docs/spec-compiler-part-3-mem.md","roles":["applicability","context"],"text":"One vector addressed memory actor is one canonical firing. Its active lanes do\nnot create independent frontier records or an implicit lane order.\n`P(access)` is the conservative union of alias partitions that any active lane\nmay access. A dynamic mask or address vector cannot weaken that set merely\nbecause one observed execution disables a lane. A statically proven all-zero\nmask may be simplified by an ordinary semantics-preserving Dataflow rewrite;\notherwise the firing retains its explicit `ctrl` and `done` obligations.","why":"The sampled output obligation with its governing context: one vector addressed memory actor is one canonical firing that retains its explicit ctrl and done obligations; determines both the selection of vector addressed actors and the ctrl/done assertions."},{"file_sha256":"6410a79f49a8948c0858239ee95ae88854c74469afe91ec0e22773de50fba131","kind":"documentation_input","lines":"470-493","path":"docs/spec-compiler-part-3-mem.md","roles":["input_well_formedness"],"text":"The owner rejects before mutation when:\n\n* raw or unverifiably owned parallel SCF reaches a graph;\n* an effectful or unmodeled nested operation reaches a graph;\n* a residual LLVM load, store, atomicrmw, cmpxchg, fence, memcpy, memmove, or\n  memset remains after\n  normalization and therefore has no explicit completion event;\n* a source memory access has not been normalized to the canonical linear\n  memory-space form required by its scalar or vector Dataflow actor;\n* structured control carries a memref result or memref loop state;\n* the graph entry lacks the leading `none` execution value.\n\nLLVM memcpy, memmove, and memset intrinsics are expanded into their exact\nstructured loop semantics before ownership selection. Supported LLVM\nload/store (including volatile and atomic contracts), `atomicrmw`, `cmpxchg`,\nand `fence` forms are then normalized before recursive region lowering, after\nwhich the same frontier rules apply. LLVM target-specific sync scopes without\na compiler-target owner and atomic accesses without an explicit power-of-two\nsource alignment fail closed. Every residual raw LLVM memory operation fails\nclosed. The finalized-graph gate also rejects residual\n`memref.load`/`memref.store`, `memref.get_global`, raw pointer arithmetic,\npointer-bearing operations, `builtin.unrealized_conversion_cast`, and unknown\nmemory-capability producers. An unsupported effectful operation inside a\nstructured region must likewise fail closed instead of being hoisted.","why":"Pre-mutation rejection list and finalized-graph gate (raw parallel SCF, residual LLVM memory ops, unnormalized accesses, memref results on structured control, missing leading none entry value, residual memref.load/store at the gate); the grammar avoids every rejected construct and always emits the leading none graph-entry value."},{"file_sha256":"f4e60b2e62b496c3714437bd100ab5236540abebd3685dfbd25eeddb37cb7160","kind":"language_definition","lines":"412-527","path":"include/Dataflow/IR/DataflowOps.td","roles":["input_construction","input_well_formedness"],"text":"//===----------------------------------------------------------------------===//\n// Memory Ops\n//\n// Streaming accesses against a memref, orchestrated by none-typed ctrl / done\n// tokens. The memref's element type constrains the element data type or the\n// access vector's element type.\n//===----------------------------------------------------------------------===//\n\n// The canonical memory actors. Each projects the standard MLIR memory effects\n// through the one shared implementation in `DataflowMemoryContracts.cpp`; no\n// actor classifies its own effects. That projection names the memory operand\n// for the addressed access and reads the atomic and volatile facts back from\n// the actor's one aggregate contract to add conservative unbound effects.\nclass Dataflow_MemoryActorOp<string mnemonic, list<Trait> traits = []>\n    : Dataflow_Op<mnemonic, !listconcat(traits, [\n        CanonicalDataflowActor,\n        DeclareOpInterfaceMethods<MemoryEffectsOpInterface>])> {\n  let extraClassDefinition = [{\n    void $cppClass::getEffects(\n        ::llvm::SmallVectorImpl<::mlir::MemoryEffects::EffectInstance>\n            &effects) {\n      ::dataflow::semantics::getMemoryActorEffects(getOperation(), effects);\n    }\n  }];\n}\n\ndef Dataflow_LoadOp : Dataflow_MemoryActorOp<\"load\"> {\n  let summary = \"streaming element, contiguous vector, or gather load\";\n  let description = [{\n    On the simultaneous arrival of an address token and a `%ctrl : none`\n    token, consumes both and fires one memory actor.\n    A result type exactly equal to the memref element type loads one\n    memory element, including when that element type is itself a vector.\n    Otherwise, a fixed-size vector result of any positive rank loads that many\n    elements in canonical row-major lane order, contiguously from a scalar\n    `%addr : index` or, with a same-shape `%addr : vector<...xindex>`, one\n    element per lane from the corresponding element-index address. A vector\n    access requires the memref element type as its vector element type.\n\n    An optional same-shape `i1` mask restricts a vector load to active lanes.\n    Inactive lanes do not access memory and are deterministically zero-filled.\n    After all active lanes retire, the op emits one data token and one `none`\n    token on `%done`.\n\n    The optional `contract` attribute is this actor's single\n    `MemoryAccessContract`; its absence is the canonical plain non-volatile\n    contract.\n  }];\n\n  let arguments = (ins AnyMemRef:$mem, AnyType:$addr, NoneType:$ctrl,\n                       Optional<AnyVectorOfAnyRank>:$mask,\n                       OptionalAttr<Dataflow_MemoryAccessContract>:$contract);\n  let results = (outs AnyType:$data, NoneType:$done);\n\n  let hasCustomAssemblyFormat = 1;\n  let hasVerifier = 1;\n  let builders = [\n    OpBuilder<(ins\n        \"::mlir::Type\":$data,\n        \"::mlir::Type\":$done,\n        \"::mlir::Value\":$mem,\n        \"::mlir::Value\":$addr,\n        \"::mlir::Value\":$ctrl)>,\n    OpBuilder<(ins\n        \"::mlir::Value\":$mem,\n        \"::mlir::Value\":$addr,\n        \"::mlir::Value\":$ctrl)>\n  ];\n}\n\ndef Dataflow_StoreOp : Dataflow_MemoryActorOp<\"store\"> {\n  let summary = \"streaming element, contiguous vector, or scatter store\";\n  let description = [{\n    On the simultaneous arrival of an address token, a `%data` value\n    and a `%ctrl : none`, consumes all three and fires one memory actor.\n    Data whose type exactly equals the memref element type writes one\n    memory element, including when that element type is itself a vector.\n    Otherwise, fixed-size vector data of any positive rank writes that many\n    elements in canonical row-major lane order, contiguously from a scalar\n    `%addr : index` or, with a same-shape `%addr : vector<...xindex>`, one\n    element per lane. A vector access requires the memref element type as its\n    vector element type.\n\n    An optional same-shape `i1` mask restricts a vector store to active lanes.\n    Inactive lanes do not access memory. After all active lanes retire, the op\n    emits one `none` token on `%done`.\n\n    The optional `contract` attribute is this actor's single\n    `MemoryAccessContract`; its absence is the canonical plain non-volatile\n    contract.\n  }];\n\n  let arguments = (ins AnyMemRef:$mem, AnyType:$addr, AnyType:$data,\n                       NoneType:$ctrl,\n                       Optional<AnyVectorOfAnyRank>:$mask,\n                       OptionalAttr<Dataflow_MemoryAccessContract>:$contract);\n  let results = (outs NoneType:$done);\n\n  let hasCustomAssemblyFormat = 1;\n  let hasVerifier = 1;\n  let builders = [\n    OpBuilder<(ins\n        \"::mlir::Type\":$done,\n        \"::mlir::Value\":$mem,\n        \"::mlir::Value\":$addr,\n        \"::mlir::Value\":$data,\n        \"::mlir::Value\":$ctrl)>,\n    OpBuilder<(ins\n        \"::mlir::Value\":$mem,\n        \"::mlir::Value\":$addr,\n        \"::mlir::Value\":$data,\n        \"::mlir::Value\":$ctrl)>\n  ];\n}","why":"TableGen definition of the canonical memory actors dataflow.load and dataflow.store: operand order (mem, addr, ctrl:none, optional mask) and result order (data, done:none / done:none), which fixes both the gather/scatter input spelling and the operand/result positions read by the postcondition."},{"file_sha256":"f4e60b2e62b496c3714437bd100ab5236540abebd3685dfbd25eeddb37cb7160","kind":"language_definition","lines":"839-950","path":"include/Dataflow/IR/DataflowOps.td","roles":["input_well_formedness"],"text":"def Dataflow_GraphOp : Dataflow_Op<\"graph\", [\n    IsolatedFromAbove,\n    HasParent<\"::mlir::ModuleOp\">,\n    SingleBlockImplicitTerminator<\"GraphReturnOp\">,\n    FunctionOpInterface,\n    RecursiveMemoryEffects,\n    DeclareOpInterfaceMethods<RegionKindInterface>\n]> {\n  let summary = \"Symbol-bearing function-like SpatialCore graph definition\";\n  let description = [{\n    Module-scope, function-like callable holding the SpatialCore body\n    of a leaf dataflow graph. It does not itself execute; one or more\n    `dataflow.graph.launch` ops materialise launches of it inside the\n    body of a `dataflow.thread` definition.\n\n    `function_type` contains only application payload ports. Normalized\n    `input_segments` and `result_segments` classify those payloads as value,\n    stream, and memory ports. The body's distinguished leading `none` block\n    argument is the invocation start protocol endpoint, while launch `done`\n    is derived exclusively from `dataflow.graph.return.complete`; neither is\n    stored in the function type.\n\n    This is the only canonical graph definition surface.\n  }];\n\n  let arguments = (ins\n      SymbolNameAttr:$sym_name,\n      TypeAttrOf<FunctionType>:$function_type,\n      DenseI32ArrayAttr:$input_segments,\n      DenseI32ArrayAttr:$result_segments,\n      OptionalAttr<StrAttr>:$sym_visibility,\n      OptionalAttr<DictArrayAttr>:$arg_attrs,\n      OptionalAttr<DictArrayAttr>:$res_attrs);\n\n  let regions = (region SizedRegion<1>:$body);\n\n  let hasCustomAssemblyFormat = 1;\n  let hasVerifier = 1;\n\n  let builders = [\n    OpBuilder<(ins\n        \"::llvm::StringRef\":$name,\n        \"::mlir::FunctionType\":$type,\n        CArg<\"::llvm::ArrayRef<::mlir::NamedAttribute>\", \"{}\">:$attrs)>\n  ];\n\n  let extraClassDeclaration = [{\n    /// FunctionOpInterface methods.\n    ::llvm::ArrayRef<::mlir::Type> getArgumentTypes() {\n      return getFunctionType().getInputs();\n    }\n    ::llvm::ArrayRef<::mlir::Type> getResultTypes() {\n      return getFunctionType().getResults();\n    }\n    ::mlir::Region *getCallableRegion() {\n      return isExternal() ? nullptr : &getBody();\n    }\n    bool isExternal() { return getBody().empty(); }\n    ::mlir::BlockArgument getStart();\n    ::llvm::ArrayRef<int32_t> getInputSegmentSizes();\n    ::llvm::ArrayRef<int32_t> getResultSegmentSizes();\n    GraphPortKind getInputPortKind(unsigned index);\n    GraphPortKind getResultPortKind(unsigned index);\n    ::llvm::LogicalResult verifyBody() {\n      if (isExternal())\n        return ::mlir::success();\n      ::mlir::Block &entry = getBody().front();\n      ::llvm::ArrayRef<::mlir::Type> inputs = getFunctionType().getInputs();\n      if (entry.getNumArguments() != inputs.size() + 1)\n        return emitOpError(\"entry block must have one start argument plus \")\n               << inputs.size() << \" application inputs\";\n      if (!::llvm::isa<::mlir::NoneType>(entry.getArgument(0).getType()))\n        return emitOpError(\"entry block argument #0 must be start type none\");\n      for (size_t i = 0, e = inputs.size(); i < e; ++i) {\n        if (entry.getArgument(i + 1).getType() != inputs[i])\n          return emitOpError(\"entry block argument #\")\n                 << (i + 1) << \" type \"\n                 << entry.getArgument(i + 1).getType()\n                 << \" must match function input type \" << inputs[i];\n      }\n      return ::mlir::success();\n    }\n  }];\n}\n\ndef Dataflow_GraphReturnOp : Dataflow_Op<\"graph.return\", [\n    AttrSizedOperandSegments,\n    Terminator,\n    ParentOneOf<[\"::dataflow::GraphOp\"]>,\n    Pure\n]> {\n  let summary = \"Terminator for a dataflow.graph body\";\n  let description = [{\n    Structurally declares the enclosing graph's value, stream, and memory\n    outputs together with its mandatory retirement frontier. `complete` is\n    an unordered all-of set of one or more `none` values; the launch `done`\n    event is derived from that set and is not itself a return operand.\n\n    The compact assembly form `%complete, %values... : none, types...` is\n    retained for the common case with one completion witness and no stream\n    or memory outputs. Other shapes print all four named segments.\n  }];\n\n  let arguments = (ins\n      Variadic<AnyType>:$values,\n      Variadic<AnyType>:$streams,\n      Variadic<AnyType>:$memories,\n      Variadic<NoneType>:$complete);\n\n  let hasCustomAssemblyFormat = 1;\n\n  let skipDefaultBuilders = 1;","why":"dataflow.graph and dataflow.graph.return definitions: the leading none start block argument, the input_segments/result_segments value-stream-memory classification, and the compact return form used by every sampled graph."},{"file_sha256":"8df97a8d593919ad549cd11f13281c367f306cb3dc073d1a2793b28f8182db2a","kind":"verifier","lines":"36-59,116-146","path":"lib/Frontend/Lowering/RankedMemRefLowering.cpp","roles":["input_well_formedness"],"text":"::mlir::LogicalResult checkRankedVectorTransfer(::mlir::Operation *operation,\n                                                ::mlir::MemRefType memory,\n                                                ::mlir::ValueRange indices,\n                                                ::mlir::VectorType vector,\n                                                ::mlir::AffineMap permutation,\n                                                ::mlir::ArrayAttr inBounds,\n                                                unsigned indexBits) {\n  ::llvm::SmallVector<std::int64_t> strides;\n  std::int64_t offset = 0;\n  if (vector.isScalable() || vector.getRank() != 1 || memory.getRank() != 1 ||\n      memory.getElementType() != vector.getElementType() ||\n      ::mlir::failed(memory.getStridesAndOffset(strides, offset)) ||\n      strides.size() != 1 || strides.front() != 1 ||\n      permutation !=\n          ::mlir::AffineMap::getMultiDimIdentityMap(1, operation->getContext()))\n    return operation->emitError(\n        \"loom-lower-graph-memory: vector transfer requires a fixed rank-one \"\n        \"minor-identity access over a unit-stride scalar memref\");\n  if (!allTransferDimensionsInBounds(inBounds))\n    return operation->emitError(\n        \"loom-lower-graph-memory: vector transfer requires every lane to be \"\n        \"proven in-bounds\");\n  return checkRankedMemRefAccess(operation, memory, indices, indexBits);\ncheckRankedVectorTransferRead(::mlir::vector::TransferReadOp read,\n                              unsigned indexBits) {\n  auto memory = ::llvm::dyn_cast<::mlir::MemRefType>(read.getBase().getType());\n  if (!memory)\n    return read.emitOpError(\n        \"loom-lower-graph-memory: vector read requires a ranked memref base\");\n  const bool paddingCanBeObserved =\n      read.getMask() && !resultIsMaskGuarded(read);\n  if (paddingCanBeObserved &&\n      !::mlir::matchPattern(read.getPadding(), ::mlir::m_Zero()))\n    return read.emitOpError(\n        \"loom-lower-graph-memory: observable vector read padding must be \"\n        \"zero\");\n  return checkRankedVectorTransfer(\n      read, memory, read.getIndices(), read.getVectorType(),\n      read.getPermutationMap(), read.getInBounds(), indexBits);\n}\n\n::mlir::LogicalResult\ncheckRankedVectorTransferWrite(::mlir::vector::TransferWriteOp write,\n                               unsigned indexBits) {\n  auto memory = ::llvm::dyn_cast<::mlir::MemRefType>(write.getBase().getType());\n  if (!memory || write.getResult())\n    return write.emitOpError(\n        \"loom-lower-graph-memory: vector write requires a ranked memref base\");\n  return checkRankedVectorTransfer(\n      write, memory, write.getIndices(), write.getVectorType(),\n      write.getPermutationMap(), write.getInBounds(), indexBits);\n}\n\n::mlir::Value buildExactLinearIndex(::mlir::OpBuilder &builder,","why":"Acceptance conditions for vector transfers in a graph: fixed rank-one minor-identity access over a unit-stride rank-one memref whose element type equals the vector element type, every lane proven in-bounds, and zero padding when masked padding is observable; the grammar emits exactly this shape."},{"file_sha256":"4295a7f0089a5b35f7f7f538032b31f51ca3966d4279faa030a2d493a8f76385","kind":"implementation","lines":"1390-1440","path":"lib/Frontend/Lowering/GraphRegionLowering.cpp","roles":["applicability"],"text":"void lowerVectorRead(::mlir::vector::TransferReadOp read,\n                       ::mlir::Value execution, MemoryState &memory) {\n    ::llvm::SmallVector<unsigned, 4> membership = partitionsFor(read);\n    ::mlir::Value ctrl = readControl(read, execution, memory);\n    setInsertionPoint(read.getLoc());\n    auto memoryType =\n        ::llvm::cast<::mlir::MemRefType>(read.getBase().getType());\n    ::mlir::Value address = ::loom::lowering::detail::buildExactLinearIndex(\n        builder, read.getLoc(), memoryType, read.getIndices(), execution);\n    auto lowered = ::dataflow::LoadOp::create(\n        builder, read.getLoc(), read.getVectorType(), builder.getNoneType(),\n        read.getBase(), address, ctrl, read.getMask(), ::mlir::Attribute{});\n    partitionsByAccess.try_emplace(lowered, std::move(membership));\n    read.getResult().replaceAllUsesWith(lowered.getData());\n    updateReadFrontiers(lowered, lowered.getDone(), memory);\n    read.erase();\n  }\n\n  void lowerVectorWrite(::mlir::vector::TransferWriteOp write,\n                        ::mlir::Value execution, MemoryState &memory) {\n    ::llvm::SmallVector<unsigned, 4> membership = partitionsFor(write);\n    ::mlir::Value ctrl = writeControl(write, execution, memory);\n    setInsertionPoint(write.getLoc());\n    auto memoryType =\n        ::llvm::cast<::mlir::MemRefType>(write.getBase().getType());\n    ::mlir::Value address = ::loom::lowering::detail::buildExactLinearIndex(\n        builder, write.getLoc(), memoryType, write.getIndices(), execution);\n    auto lowered = ::dataflow::StoreOp::create(\n        builder, write.getLoc(), builder.getNoneType(), write.getBase(),\n        address, write.getValueToStore(), ctrl, write.getMask(),\n        ::mlir::Attribute{});\n    partitionsByAccess.try_emplace(lowered, std::move(membership));\n    updateWriteFrontiers(lowered, lowered.getDone(), memory);\n    write.erase();\n  }\n\n  void lowerDataflowLoad(::dataflow::LoadOp load, ::mlir::Value execution,\n                         MemoryState &memory) {\n    load.getCtrlMutable().assign(readControl(load, execution, memory));\n    updateReadFrontiers(load, load.getDone(), memory);\n    if (load->getBlock() != &entry)\n      load->moveBefore(anchor);\n  }\n\n  void lowerDataflowStore(::dataflow::StoreOp store, ::mlir::Value execution,\n                          MemoryState &memory) {\n    store.getCtrlMutable().assign(writeControl(store, execution, memory));\n    updateWriteFrontiers(store, store.getDone(), memory);\n    if (store->getBlock() != &entry)\n      store->moveBefore(anchor);\n  }","why":"Shows that vector.transfer_read/transfer_write become vector-addressed dataflow.load/store actors and that pre-existing dataflow.load/store actors only get their ctrl reassigned, establishing which output operations the sampled obligation governs."},{"file_sha256":"11d4b44ce36afb532b1ba720012841c38babad2962aadee232609a04fc28dbc4","kind":"test","lines":"1-23","path":"test/raise/scf-to-dfg-memory-frontier.mlir","roles":["input_construction"],"text":"// RUN: loom-raise-opt --split-input-file --loom-lower-graph-memory %s | FileCheck %s\n\n// CHECK-LABEL: dataflow.graph private @frontier_straight\n// CHECK: %[[R0:.*]], %[[D0:.*]] = dataflow.load %arg4[%arg1] %arg0 : memref<16xi32>\n// CHECK: %[[R1:.*]], %[[D1:.*]] = dataflow.load %arg4[%arg2] %arg0 : memref<16xi32>\n// CHECK: %[[WRITE:.*]] = dataflow.store %arg4[%arg1] %arg3 [[READS:%[^# ]+]]#0 : memref<16xi32>\n// CHECK: %[[R2:.*]], %[[D2:.*]] = dataflow.load %arg4[%arg2] %[[WRITE]] : memref<16xi32>\n// CHECK: [[READS]]:2 = dataflow.sync %[[D0]], %[[D1]] : (none, none) -> (none, none)\n// CHECK: %[[RB:.*]], %[[DB:.*]] = dataflow.load %arg5[%arg1] %[[WRITE]] : memref<16xi32>\n// CHECK: %[[RETIRE:.*]]:2 = dataflow.sync %[[D2]], %[[DB]] : (none, none) -> (none, none)\n// CHECK: dataflow.graph.return %[[RETIRE]]#0 : none\ndataflow.graph private @frontier_straight(\n    %start: none, %i: index, %j: index, %value: i32,\n    %a: memref<16xi32>, %b: memref<16xi32>) -> ()\n    attributes {input_segments = array<i32: 3, 0, 2>,\n                result_segments = array<i32: 0, 0, 0>} {\n  %r0, %read0_done = dataflow.load %a[%i] %start : memref<16xi32>\n  %r1, %read1_done = dataflow.load %a[%j] %start : memref<16xi32>\n  %write_done = dataflow.store %a[%i] %value %start : memref<16xi32>\n  %r2, %read2_done = dataflow.load %a[%j] %start : memref<16xi32>\n  %rb = memref.load %b[%i] : memref<16xi32>\n  dataflow.graph.return %start : none\n}","why":"Non-normative evidence for the accepted module spelling under this pass: a private dataflow.graph with a leading none start argument, may-alias memref inputs, memory leaves in the body, and dataflow.graph.return."},{"file_sha256":"d161de7a4a08f9902236e14b73808fc9caeadf88e4b2f2e15d61000cb648ebb0","kind":"example","lines":"69-80","path":"test/raise/scf-to-dfg-graph-memory.mlir","roles":["input_construction"],"text":"//--- ranked.mlir\nmodule {\n  dataflow.graph private @rank3_row_major(\n      %start: none, %i: index, %j: index, %k: index,\n      %memory: memref<3x5x7xf32>) -> ()\n      attributes {input_segments = array<i32: 3, 0, 1>,\n                  result_segments = array<i32: 0, 0, 0>} {\n    %value = memref.load %memory[%i, %j, %k] : memref<3x5x7xf32>\n    memref.store %value, %memory[%i, %j, %k] : memref<3x5x7xf32>\n    dataflow.graph.return %start : none\n  }\n}","why":"One accepted spelling of the graph attribute dictionary (input_segments/result_segments arrays) used verbatim in shape by the generated graphs."},{"file_sha256":"2eff2258b85959a00302a5bee9240d30ea330a85061eaedae51a3fad2f9e37f4","kind":"example","lines":"46-64","path":"test/dataflow/unit/load/valid.mlir","roles":["input_construction"],"text":"// CHECK-LABEL: @load_masked_vector_i32\nfunc.func @load_masked_vector_i32(\n    %mem: memref<10xi32>, %addr: index, %mask: vector<4xi1>, %ctrl: none)\n    -> (vector<4xi32>, none) {\n  // CHECK: dataflow.load %{{.*}}[%{{.*}}] %{{.*}} mask %{{.*}} : memref<10xi32>, vector<4xi32>\n  %data, %done = dataflow.load %mem[%addr] %ctrl mask %mask\n      : memref<10xi32>, vector<4xi32>\n  return %data, %done : vector<4xi32>, none\n}\n\n// CHECK-LABEL: @load_gather_i32\nfunc.func @load_gather_i32(\n    %mem: memref<10xi32>, %addr: vector<4xindex>, %mask: vector<4xi1>,\n    %ctrl: none) -> (vector<4xi32>, none) {\n  // CHECK: dataflow.load %{{.*}}[%{{.*}}] %{{.*}} mask %{{.*}} : memref<10xi32>, vector<4xindex>, vector<4xi32>\n  %data, %done = dataflow.load %mem[%addr] %ctrl mask %mask\n      : memref<10xi32>, vector<4xindex>, vector<4xi32>\n  return %data, %done : vector<4xi32>, none\n}","why":"Accepted textual spelling of masked contiguous and gather dataflow.load, used for the gather alternative emitted directly by the grammar."},{"file_sha256":"3b048f487c94803ff885832a4d9ade824e1f58c396e2838dac0cd0628c145333","kind":"example","lines":"46-64","path":"test/dataflow/unit/store/valid.mlir","roles":["input_construction"],"text":"// CHECK-LABEL: @store_masked_vector_i32\nfunc.func @store_masked_vector_i32(\n    %mem: memref<10xi32>, %addr: index, %data: vector<4xi32>,\n    %mask: vector<4xi1>, %ctrl: none) -> none {\n  // CHECK: dataflow.store %{{.*}}[%{{.*}}] %{{.*}} %{{.*}} mask %{{.*}} : memref<10xi32>, vector<4xi32>\n  %done = dataflow.store %mem[%addr] %data %ctrl mask %mask\n      : memref<10xi32>, vector<4xi32>\n  return %done : none\n}\n\n// CHECK-LABEL: @store_multi_rank_scatter\nfunc.func @store_multi_rank_scatter(\n    %mem: memref<10xi32>, %addr: vector<2x3xindex>, %data: vector<2x3xi32>,\n    %mask: vector<2x3xi1>, %ctrl: none) -> none {\n  // CHECK: dataflow.store %{{.*}}[%{{.*}}] %{{.*}} %{{.*}} mask %{{.*}} : memref<10xi32>, vector<2x3xindex>, vector<2x3xi32>\n  %done = dataflow.store %mem[%addr] %data %ctrl mask %mask\n      : memref<10xi32>, vector<2x3xindex>, vector<2x3xi32>\n  return %done : none\n}","why":"Accepted textual spelling of masked contiguous and scatter dataflow.store, used for the scatter alternative emitted directly by the grammar."}],"primary_bundle_sha256":"82b7fabd40d78b956f5f6ff6dffecb7e5318aa105f1072eb2a3c349cab37de52","project":"PolyArch/loom","revision":"48615bc5925ef4b9db8b4550b5d4322933cf4b7b","schema":"spectriad.authoring-context/v1","selection_sha256":"c33a8a8330f1ceb49ed04550b36e928f86ea79b389eb91a24fb818168e05b833"}