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input.generic.mlir

"builtin.module"() ({
  "llvm.func"() <{CConv = #llvm.cconv<ccc>, function_type = !llvm.func<void (i8)>, linkage = #llvm.linkage<external>, passthrough = ["nounwind"], sym_name = "zero_counts_0", unnamed_addr = 0 : i64, visibility_ = 0 : i64}> ({
  ^bb0(%arg2: i8):
    %6 = "llvm.intr.ctlz"(%arg2) <{is_zero_poison = true}> : (i8) -> i8
    %7 = "llvm.intr.ctlz"(%arg2) <{is_zero_poison = false}> : (i8) -> i8
    %8 = "llvm.intr.cttz"(%arg2) <{is_zero_poison = true}> : (i8) -> i8
    %9 = "llvm.and"(%arg2, %arg2) : (i8, i8) -> i8
    "llvm.return"() : () -> ()
  }) : () -> ()
  "llvm.func"() <{CConv = #llvm.cconv<ccc>, function_type = !llvm.func<void (vector<4xi32>)>, linkage = #llvm.linkage<external>, passthrough = ["nounwind"], sym_name = "zero_counts_1", unnamed_addr = 0 : i64, visibility_ = 0 : i64}> ({
  ^bb0(%arg1: vector<4xi32>):
    %3 = "llvm.intr.cttz"(%arg1) <{is_zero_poison = true}> : (vector<4xi32>) -> vector<4xi32>
    %4 = "llvm.intr.cttz"(%arg1) <{is_zero_poison = true}> : (vector<4xi32>) -> vector<4xi32>
    %5 = "llvm.intr.cttz"(%arg1) <{is_zero_poison = true}> : (vector<4xi32>) -> vector<4xi32>
    "llvm.return"() : () -> ()
  }) : () -> ()
  "llvm.func"() <{CConv = #llvm.cconv<ccc>, function_type = !llvm.func<void (i8)>, linkage = #llvm.linkage<external>, passthrough = [["no-trapping-math", "true"]], sym_name = "zero_counts_2", target_cpu = "generic", unnamed_addr = 0 : i64, visibility_ = 0 : i64}> ({
  ^bb0(%arg0: i8):
    %0 = "llvm.mul"(%arg0, %arg0) <{overflowFlags = 0 : i32}> : (i8, i8) -> i8
    %1 = "llvm.intr.ctlz"(%arg0) <{is_zero_poison = false}> : (i8) -> i8
    %2 = "llvm.intr.ctlz"(%arg0) <{is_zero_poison = false}> : (i8) -> i8
    "llvm.return"() : () -> ()
  }) : () -> ()
}) : () -> ()