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test.patch

diff --git a/test/raise/spectriad-mlir-stage-13-v1.mlir b/test/raise/spectriad-mlir-stage-13-v1.mlir
new file mode 100644
--- /dev/null
+++ b/test/raise/spectriad-mlir-stage-13-v1.mlir
@@ -0,0 +1,35 @@
+// RUN: loom-raise-opt --loom-lower-graph-memory --mlir-print-op-generic %s | FileCheck %s
+
+module attributes {
+  llvm.data_layout = "e-p:64:64",
+  dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 64>>
+} {
+  dataflow.graph private @source_memory_graph(
+      %start: none, %base: !llvm.ptr, %expected: i32, %desired: i32,
+      %index: i64, %cond: i1) -> ()
+      attributes {input_segments = array<i32: 5, 0, 0>,
+                  result_segments = array<i32: 0, 0, 0>} {
+    %ptr = llvm.getelementptr inbounds %base[%index]
+        : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
+    llvm.store %desired, %ptr atomic seq_cst {alignment = 4 : i64} : i32, !llvm.ptr
+    llvm.fence syncscope("system") release
+    %val2 = llvm.load volatile %ptr {alignment = 8 : i64} : !llvm.ptr -> i32
+    %rmw3 = llvm.atomicrmw _xor %ptr, %desired monotonic {alignment = 8 : i64} : !llvm.ptr, i32
+    %rmw4 = llvm.atomicrmw umin %ptr, %desired syncscope("singlethread") seq_cst {alignment = 4 : i64} : !llvm.ptr, i32
+    dataflow.graph.return %start : none
+  }
+}
+
+// CHECK: "builtin.module"() ({
+// CHECK-NEXT:   "dataflow.graph"() <{function_type = (!llvm.ptr, i32, i32, i64, i1, memref<?xi32>) -> (), input_segments = array<i32: 5, 0, 1>, result_segments = array<i32: 0, 0, 0>, sym_name = "source_memory_graph", sym_visibility = "private"}> ({
+// CHECK-NEXT:   ^bb0(%arg0: none, %arg1: !llvm.ptr, %arg2: i32, %arg3: i32, %arg4: i64, %arg5: i1, %arg6: memref<?xi32>):
+// CHECK-NEXT:     %0 = "llvm.getelementptr"(%arg1, %arg4) <{elem_type = !llvm.array<4 x i8>, noWrapFlags = 3 : i32, rawConstantIndices = array<i32: -2147483648>}> : (!llvm.ptr, i64) -> !llvm.ptr
+// CHECK-NEXT:     %1 = "dataflow.store"(%arg6, %0, %arg3, %arg0) <{contract = #dataflow.atomic_access<ordering = seq_cst, sync_scope = <system>, source_alignment_bytes = 4>}> : (memref<?xi32>, !llvm.ptr, i32, none) -> none
+// CHECK-NEXT:     %2 = "dataflow.fence"(%1) <{contract = #dataflow.fence_contract<ordering = release, sync_scope = <system>>}> : (none) -> none
+// CHECK-NEXT:     %3:2 = "dataflow.load"(%arg6, %0, %2) <{contract = #dataflow.plain_access<is_volatile = true>}> : (memref<?xi32>, !llvm.ptr, none) -> (i32, none)
+// CHECK-NEXT:     %4:2 = "dataflow.atomic_rmw"(%arg6, %0, %arg3, %3#1) <{contract = #dataflow.rmw_contract<kind = xor, access = <ordering = monotonic, sync_scope = <system>, source_alignment_bytes = 8>>}> : (memref<?xi32>, !llvm.ptr, i32, none) -> (i32, none)
+// CHECK-NEXT:     %5:2 = "dataflow.atomic_rmw"(%arg6, %0, %arg3, %4#1) <{contract = #dataflow.rmw_contract<kind = umin, access = <ordering = seq_cst, sync_scope = <single_thread>, source_alignment_bytes = 4>>}> : (memref<?xi32>, !llvm.ptr, i32, none) -> (i32, none)
+// CHECK-NEXT:     "dataflow.graph.return"(%5#1) <{operandSegmentSizes = array<i32: 0, 0, 0, 1>}> : (none) -> ()
+// CHECK-NEXT:   }) : () -> ()
+// CHECK-NEXT: }) {dlti.dl_spec = #dlti.dl_spec<index = 64 : i64>, llvm.data_layout = "e-p:64:64"} : () -> ()
+// CHECK-EMPTY: