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test.patch

diff --git a/test/raise/spectriad-mlir-stage-13-v1.mlir b/test/raise/spectriad-mlir-stage-13-v1.mlir
new file mode 100644
--- /dev/null
+++ b/test/raise/spectriad-mlir-stage-13-v1.mlir
@@ -0,0 +1,45 @@
+// RUN: loom-raise-opt --loom-lower-graph-memory %s | FileCheck %s
+
+module attributes {
+  llvm.data_layout = "e-p:64:64",
+  dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 64>>
+} {
+  dataflow.graph private @source_memory_graph(
+      %start: none, %base: !llvm.ptr, %expected: i32, %desired: i32,
+      %index: i64, %cond: i1) -> ()
+      attributes {input_segments = array<i32: 5, 0, 0>,
+                  result_segments = array<i32: 0, 0, 0>} {
+    %ptr = llvm.getelementptr inbounds %base[%index]
+        : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
+    scf.if %cond {
+    %val0 = llvm.load %ptr atomic seq_cst {alignment = 4 : i64} : !llvm.ptr -> i32
+    %rmw1 = llvm.atomicrmw xchg %ptr, %desired acquire {alignment = 4 : i64} : !llvm.ptr, i32
+    %rmw2 = llvm.atomicrmw umax %ptr, %desired syncscope("singlethread") seq_cst {alignment = 8 : i64} : !llvm.ptr, i32
+    llvm.fence syncscope("system") release
+    llvm.store %desired, %ptr atomic seq_cst {alignment = 4 : i64} : i32, !llvm.ptr
+    }
+    dataflow.graph.return %start : none
+  }
+}
+
+// CHECK: module attributes {dlti.dl_spec = #dlti.dl_spec<index = 64 : i64>, llvm.data_layout = "e-p:64:64"} {
+// CHECK-NEXT:   dataflow.graph private @source_memory_graph(%arg0: none, %arg1: !llvm.ptr, %arg2: i32, %arg3: i32, %arg4: i64, %arg5: i1, %arg6: memref<?xi32>) -> () attributes {input_segments = array<i32: 5, 0, 1>, result_segments = array<i32: 0, 0, 0>} {
+// CHECK-NEXT:     %0 = llvm.getelementptr inbounds %arg1[%arg4] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
+// CHECK-NEXT:     %1:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %2:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %3:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %4:2 = dataflow.demux %arg5, %0 : (i1, !llvm.ptr) -> (!llvm.ptr, !llvm.ptr)
+// CHECK-NEXT:     %5:2 = dataflow.demux %arg5, %arg3 : (i1, i32) -> (i32, i32)
+// CHECK-NEXT:     %6:2 = dataflow.sync %1#1, %2#1 : (none, none) -> (none, none)
+// CHECK-NEXT:     %7:2 = dataflow.sync %3#1, %done : (none, none) -> (none, none)
+// CHECK-NEXT:     %data, %done = dataflow.load %arg6[%4#1] %6#0 {contract = #dataflow.atomic_access<ordering = seq_cst, sync_scope = <system>, source_alignment_bytes = 4>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %old, %done_0 = dataflow.atomic_rmw %arg6[%4#1] %5#1 %7#0 {contract = #dataflow.rmw_contract<kind = xchg, access = <ordering = acquire, sync_scope = <system>, source_alignment_bytes = 4>>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %old_1, %done_2 = dataflow.atomic_rmw %arg6[%4#1] %5#1 %done_0 {contract = #dataflow.rmw_contract<kind = umax, access = <ordering = seq_cst, sync_scope = <single_thread>, source_alignment_bytes = 8>>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %8 = dataflow.fence %done_2 {contract = #dataflow.fence_contract<ordering = release, sync_scope = <system>>}
+// CHECK-NEXT:     %9 = dataflow.store %arg6[%4#1] %5#1 %8 {contract = #dataflow.atomic_access<ordering = seq_cst, sync_scope = <system>, source_alignment_bytes = 4>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %10 = dataflow.mux %arg5, %3#0, %9 : (i1, none, none) -> none
+// CHECK-NEXT:     %11 = dataflow.mux %arg5, %1#0, %8 : (i1, none, none) -> none
+// CHECK-NEXT:     dataflow.graph.return values() streams() memories() complete(%11, %10 : none, none)
+// CHECK-NEXT:   }
+// CHECK-NEXT: }
+// CHECK-EMPTY: