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test.patch

diff --git a/test/raise/spectriad-mlir-stage-13-v1.mlir b/test/raise/spectriad-mlir-stage-13-v1.mlir
new file mode 100644
--- /dev/null
+++ b/test/raise/spectriad-mlir-stage-13-v1.mlir
@@ -0,0 +1,37 @@
+// RUN: loom-raise-opt --loom-lower-graph-memory %s | FileCheck %s
+
+module attributes {
+  llvm.data_layout = "e-p:64:64",
+  dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 64>>
+} {
+  dataflow.graph private @source_memory_graph(
+      %start: none, %base: !llvm.ptr, %expected: i32, %desired: i32,
+      %index: i64, %cond: i1) -> ()
+      attributes {input_segments = array<i32: 5, 0, 0>,
+                  result_segments = array<i32: 0, 0, 0>} {
+    %ptr = llvm.getelementptr inbounds %base[%index]
+        : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
+    %rmw0 = llvm.atomicrmw _and %ptr, %desired syncscope("system") seq_cst {alignment = 8 : i64} : !llvm.ptr, i32
+    %rmw1 = llvm.atomicrmw _or %ptr, %desired syncscope("system") release {alignment = 8 : i64} : !llvm.ptr, i32
+    %val3 = llvm.load volatile %ptr {alignment = 4 : i64} : !llvm.ptr -> i32
+    %rmw4 = llvm.atomicrmw min %ptr, %desired syncscope("singlethread") monotonic {alignment = 4 : i64} : !llvm.ptr, i32
+    %pair5 = llvm.cmpxchg %ptr, %expected, %desired syncscope("singlethread") acquire acquire {alignment = 4 : i64} : !llvm.ptr, i32
+    dataflow.graph.return %start : none
+  }
+}
+
+// CHECK: module attributes {dlti.dl_spec = #dlti.dl_spec<index = 64 : i64>, llvm.data_layout = "e-p:64:64"} {
+// CHECK-NEXT:   dataflow.graph private @source_memory_graph(%arg0: none, %arg1: !llvm.ptr, %arg2: i32, %arg3: i32, %arg4: i64, %arg5: i1, %arg6: memref<?xi32>) -> () attributes {input_segments = array<i32: 5, 0, 1>, result_segments = array<i32: 0, 0, 0>} {
+// CHECK-NEXT:     %0 = llvm.getelementptr inbounds %arg1[%arg4] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
+// CHECK-NEXT:     %old, %done = dataflow.atomic_rmw %arg6[%0] %arg3 %arg0 {contract = #dataflow.rmw_contract<kind = and, access = <ordering = seq_cst, sync_scope = <system>, source_alignment_bytes = 8>>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %old_0, %done_1 = dataflow.atomic_rmw %arg6[%0] %arg3 %done {contract = #dataflow.rmw_contract<kind = or, access = <ordering = release, sync_scope = <system>, source_alignment_bytes = 8>>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %data, %done_2 = dataflow.load %arg6[%0] %done_1 {contract = #dataflow.plain_access<is_volatile = true>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %old_3, %done_4 = dataflow.atomic_rmw %arg6[%0] %arg3 %done_2 {contract = #dataflow.rmw_contract<kind = min, access = <ordering = monotonic, sync_scope = <single_thread>, source_alignment_bytes = 4>>} : memref<?xi32>, !llvm.ptr
+// CHECK-NEXT:     %old_5, %success, %done_6 = dataflow.cmpxchg %arg6[%0] %arg2 %arg3 %done_4 {contract = #dataflow.cmpxchg_contract<success_ordering = acquire, failure_ordering = acquire, sync_scope = <single_thread>, source_alignment_bytes = 4>} : memref<?xi32>, !llvm.ptr -> i1
+// CHECK-NEXT:     %1 = llvm.mlir.undef : !llvm.struct<(i32, i1)>
+// CHECK-NEXT:     %2 = llvm.insertvalue %old_5, %1[0] : !llvm.struct<(i32, i1)> 
+// CHECK-NEXT:     %3 = llvm.insertvalue %success, %2[1] : !llvm.struct<(i32, i1)> 
+// CHECK-NEXT:     dataflow.graph.return %done_6 : none
+// CHECK-NEXT:   }
+// CHECK-NEXT: }
+// CHECK-EMPTY: