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input.mlir

module attributes {
  llvm.data_layout = "e-p:64:64",
  dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 64>>
} {
  dataflow.graph private @source_memory_graph(
      %start: none, %base: !llvm.ptr, %expected: i32, %desired: i32,
      %index: i64, %cond: i1) -> ()
      attributes {input_segments = array<i32: 5, 0, 0>,
                  result_segments = array<i32: 0, 0, 0>} {
    %ptr = llvm.getelementptr inbounds %base[%index]
        : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
    llvm.fence syncscope("system") acquire
    %val1 = llvm.load %ptr : !llvm.ptr -> i32
    %val2 = llvm.load %ptr atomic syncscope("singlethread") seq_cst {alignment = 8 : i64} : !llvm.ptr -> i32
    %rmw3 = llvm.atomicrmw add %ptr, %desired seq_cst {alignment = 8 : i64} : !llvm.ptr, i32
    %val4 = llvm.load %ptr atomic syncscope("system") monotonic {alignment = 4 : i64} : !llvm.ptr -> i32
    %val5 = llvm.load %ptr : !llvm.ptr -> i32
    dataflow.graph.return %start : none
  }
}