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input.mlir

module attributes {
  llvm.data_layout = "e-p:64:64",
  dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<index, 64>>
} {
  dataflow.graph private @source_memory_graph(
      %start: none, %base: !llvm.ptr, %expected: i32, %desired: i32,
      %index: i64, %cond: i1) -> ()
      attributes {input_segments = array<i32: 5, 0, 0>,
                  result_segments = array<i32: 0, 0, 0>} {
    %ptr = llvm.getelementptr inbounds %base[%index]
        : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<4 x i8>
    llvm.fence syncscope("singlethread") seq_cst
    %val1 = llvm.load %ptr atomic seq_cst {alignment = 4 : i64} : !llvm.ptr -> i32
    llvm.store %desired, %ptr : i32, !llvm.ptr
    %pair3 = llvm.cmpxchg %ptr, %expected, %desired syncscope("system") seq_cst acquire {alignment = 8 : i64} : !llvm.ptr, i32
    llvm.store volatile %desired, %ptr {alignment = 4 : i64} : i32, !llvm.ptr
    %pair5 = llvm.cmpxchg %ptr, %expected, %desired syncscope("singlethread") release monotonic {alignment = 8 : i64} : !llvm.ptr, i32
    dataflow.graph.return %start : none
  }
}