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test.patch

diff --git a/test/raise/spectriad-mlir-stage-16-v1.mlir b/test/raise/spectriad-mlir-stage-16-v1.mlir
new file mode 100644
--- /dev/null
+++ b/test/raise/spectriad-mlir-stage-16-v1.mlir
@@ -0,0 +1,67 @@
+// RUN: loom-raise-opt --loom-lower-graph-memory %s | FileCheck %s
+
+module {
+  dataflow.graph private @view_export_0(
+      %start: none, %lb: i64, %ub: i64, %step: i64, %i: index, %c: i1, %v: i32,
+      %m: memref<4xi32>) -> (memref<?xi32>)
+      attributes {input_segments = array<i32: 6, 0, 1>,
+                  result_segments = array<i32: 0, 0, 1>} {
+    %view = memref.cast %m : memref<4xi32> to memref<?xi32>
+    scf.if %c {
+      memref.store %v, %view[%i] : memref<?xi32>
+    }
+    dataflow.graph.return values() streams()
+        memories(%view : memref<?xi32>) complete(%start : none)
+  }
+  dataflow.graph private @fresh_export_1(
+      %start: none, %lb: i64, %ub: i64, %step: i64, %i: index, %c: i1, %v: i32)
+      -> (memref<4xi32>)
+      attributes {input_segments = array<i32: 6, 0, 0>,
+                  result_segments = array<i32: 0, 0, 1>} {
+    %slot = memref.alloc() : memref<4xi32>
+    scf.for %iv = %lb to %ub step %step : i64 {
+      %idx = arith.index_cast %iv : i64 to index
+      memref.store %v, %slot[%idx] : memref<4xi32>
+    }
+    dataflow.graph.return values() streams()
+        memories(%slot : memref<4xi32>) complete(%start : none)
+  }
+}
+
+// CHECK: module {
+// CHECK-NEXT:   dataflow.graph private @view_export_0(%arg0: none, %arg1: i64, %arg2: i64, %arg3: i64, %arg4: index, %arg5: i1, %arg6: i32, %arg7: memref<4xi32>) -> memref<?xi32> attributes {input_segments = array<i32: 6, 0, 1>, result_segments = array<i32: 0, 0, 1>} {
+// CHECK-NEXT:     %cast = memref.cast %arg7 : memref<4xi32> to memref<?xi32>
+// CHECK-NEXT:     %0:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %1:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %2:2 = dataflow.demux %arg5, %arg0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %3:2 = dataflow.demux %arg5, %arg6 : (i1, i32) -> (i32, i32)
+// CHECK-NEXT:     %4:2 = dataflow.demux %arg5, %arg4 : (i1, index) -> (index, index)
+// CHECK-NEXT:     %5:2 = dataflow.sync %0#1, %2#1 : (none, none) -> (none, none)
+// CHECK-NEXT:     %6 = dataflow.store %cast[%4#1] %3#1 %5#0 : memref<?xi32>
+// CHECK-NEXT:     %7 = dataflow.mux %arg5, %2#0, %6 : (i1, none, none) -> none
+// CHECK-NEXT:     %8 = dataflow.mux %arg5, %0#0, %0#1 : (i1, none, none) -> none
+// CHECK-NEXT:     dataflow.graph.return values() streams() memories(%cast : memref<?xi32>) complete(%8, %7 : none, none)
+// CHECK-NEXT:   }
+// CHECK-NEXT:   dataflow.graph private @fresh_export_1(%arg0: none, %arg1: i64, %arg2: i64, %arg3: i64, %arg4: index, %arg5: i1, %arg6: i32) -> memref<4xi32> attributes {input_segments = array<i32: 6, 0, 0>, result_segments = array<i32: 0, 0, 1>} {
+// CHECK-NEXT:     %alloc = memref.alloc() : memref<4xi32>
+// CHECK-NEXT:     %iv, %phase = dataflow.stream %arg1, %arg2, %arg3 step add while slt : i64
+// CHECK-NEXT:     %0 = dataflow.carry %phase, %arg0, %1#1 : none
+// CHECK-NEXT:     %1:2 = dataflow.demux %phase, %0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %2 = dataflow.invariant %phase, %arg6 : i32
+// CHECK-NEXT:     %after_cond, %after_value = dataflow.gate %phase, %2 : i32
+// CHECK-NEXT:     %3:2 = dataflow.demux %after_cond, %after_value : (i1, i32) -> (i32, i32)
+// CHECK-NEXT:     %4 = dataflow.carry %phase, %arg0, %10 : none
+// CHECK-NEXT:     %5 = dataflow.carry %phase, %arg0, %10 : none
+// CHECK-NEXT:     %6:2 = dataflow.demux %phase, %4 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %7:2 = dataflow.demux %phase, %5 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %8 = arith.index_cast %iv : i64 to index
+// CHECK-NEXT:     %9:2 = dataflow.sync %1#1, %7#1 : (none, none) -> (none, none)
+// CHECK-NEXT:     %10 = dataflow.store %alloc[%8] %after_value %9#0 : memref<4xi32>
+// CHECK-NEXT:     %11 = arith.cmpi slt, %arg1, %arg2 : i64
+// CHECK-NEXT:     %12:2 = dataflow.demux %11, %1#0 : (i1, none) -> (none, none)
+// CHECK-NEXT:     %13:2 = dataflow.sync %12#1, %3#0 : (none, i32) -> (none, i32)
+// CHECK-NEXT:     %14 = dataflow.mux %11, %12#0, %13#0 : (i1, none, none) -> none
+// CHECK-NEXT:     dataflow.graph.return values() streams() memories(%alloc : memref<4xi32>) complete(%14, %7#0 : none, none)
+// CHECK-NEXT:   }
+// CHECK-NEXT: }
+// CHECK-EMPTY: