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test.patch
diff --git a/test/raise/spectriad-mlir-stage-21-v1.mlir b/test/raise/spectriad-mlir-stage-21-v1.mlir
new file mode 100644
--- /dev/null
+++ b/test/raise/spectriad-mlir-stage-21-v1.mlir
@@ -0,0 +1,115 @@
+// RUN: loom-raise-opt --loom-lower-graph-memory %s | FileCheck %s
+
+dataflow.graph private @pair_0(%start: none, %lb: i64, %ub: i64, %step: i64,
+ %a: memref<?xi32>, %b: memref<?xi32>) -> ()
+ attributes {input_segments = array<i32: 3, 0, 2>,
+ result_segments = array<i32: 0, 0, 0>} {
+ scf.for %i = %lb to %ub step %step : i64 {
+ %scaled = arith.muli %i, %step : i64
+ %idx = arith.index_cast %scaled : i64 to index
+ %ploaded = memref.load %b[%idx] : memref<?xi32>
+ memref.store %ploaded, %a[%idx] : memref<?xi32>
+ }
+ dataflow.graph.return %start : none
+}
+
+dataflow.graph private @acc_1(%start: none, %lb: i64, %ub: i64, %step: i64, %init: i32,
+ %a: memref<?xi32>) -> (i32)
+ attributes {input_segments = array<i32: 4, 0, 1>,
+ result_segments = array<i32: 1, 0, 0>} {
+ %total = scf.for %i = %lb to %ub step %step
+ iter_args(%state = %init) -> (i32) : i64 {
+ %shifted = arith.addi %i, %lb : i64
+ %idx = arith.index_cast %shifted : i64 to index
+ %aloaded = memref.load %a[%idx] : memref<?xi32>
+ %asum = arith.addi %state, %aloaded : i32
+ memref.store %asum, %a[%idx] : memref<?xi32>
+ scf.yield %asum : i32
+ }
+ dataflow.graph.return %start, %total : none, i32
+}
+
+dataflow.graph private @pair_2(%start: none, %lb: i64, %ub: i64, %step: i64,
+ %a: memref<?xi32>, %b: memref<?xi32>) -> ()
+ attributes {input_segments = array<i32: 3, 0, 2>,
+ result_segments = array<i32: 0, 0, 0>} {
+ scf.for %i = %lb to %ub step %step : i64 {
+ %idx = arith.index_cast %i : i64 to index
+ %ploaded = memref.load %b[%idx] : memref<?xi32>
+ memref.store %ploaded, %a[%idx] : memref<?xi32>
+ }
+ dataflow.graph.return %start : none
+}
+
+
+// CHECK: module {
+// CHECK-NEXT: dataflow.graph private @pair_0(%arg0: none, %arg1: i64, %arg2: i64, %arg3: i64, %arg4: memref<?xi32>, %arg5: memref<?xi32>) -> () attributes {input_segments = array<i32: 3, 0, 2>, result_segments = array<i32: 0, 0, 0>} {
+// CHECK-NEXT: %iv, %phase = dataflow.stream %arg1, %arg2, %arg3 step add while slt : i64
+// CHECK-NEXT: %0 = dataflow.carry %phase, %arg0, %1#1 : none
+// CHECK-NEXT: %1:2 = dataflow.demux %phase, %0 : (i1, none) -> (none, none)
+// CHECK-NEXT: %2 = dataflow.invariant %phase, %arg3 : i64
+// CHECK-NEXT: %after_cond, %after_value = dataflow.gate %phase, %2 : i64
+// CHECK-NEXT: %3:2 = dataflow.demux %after_cond, %after_value : (i1, i64) -> (i64, i64)
+// CHECK-NEXT: %4 = dataflow.carry %phase, %arg0, %13 : none
+// CHECK-NEXT: %5 = dataflow.carry %phase, %arg0, %13 : none
+// CHECK-NEXT: %6:2 = dataflow.demux %phase, %4 : (i1, none) -> (none, none)
+// CHECK-NEXT: %7:2 = dataflow.demux %phase, %5 : (i1, none) -> (none, none)
+// CHECK-NEXT: %8 = arith.index_cast %iv : i64 to index
+// CHECK-NEXT: %9 = arith.index_cast %after_value : i64 to index
+// CHECK-NEXT: %10 = arith.muli %8, %9 : index
+// CHECK-NEXT: %11:2 = dataflow.sync %1#1, %6#1 : (none, none) -> (none, none)
+// CHECK-NEXT: %data, %done = dataflow.load %arg5[%10] %11#0 : memref<?xi32>
+// CHECK-NEXT: %12:2 = dataflow.sync %7#1, %done : (none, none) -> (none, none)
+// CHECK-NEXT: %13 = dataflow.store %arg4[%10] %data %12#0 : memref<?xi32>
+// CHECK-NEXT: %14 = arith.cmpi slt, %arg1, %arg2 : i64
+// CHECK-NEXT: %15:2 = dataflow.demux %14, %1#0 : (i1, none) -> (none, none)
+// CHECK-NEXT: %16:2 = dataflow.sync %15#1, %3#0 : (none, i64) -> (none, i64)
+// CHECK-NEXT: %17 = dataflow.mux %14, %15#0, %16#0 : (i1, none, none) -> none
+// CHECK-NEXT: dataflow.graph.return values() streams() memories() complete(%17, %7#0 : none, none)
+// CHECK-NEXT: }
+// CHECK-NEXT: dataflow.graph private @acc_1(%arg0: none, %arg1: i64, %arg2: i64, %arg3: i64, %arg4: i32, %arg5: memref<?xi32>) -> i32 attributes {input_segments = array<i32: 4, 0, 1>, result_segments = array<i32: 1, 0, 0>} {
+// CHECK-NEXT: %iv, %phase = dataflow.stream %arg1, %arg2, %arg3 step add while slt : i64
+// CHECK-NEXT: %0 = dataflow.carry %phase, %arg0, %1#1 : none
+// CHECK-NEXT: %1:2 = dataflow.demux %phase, %0 : (i1, none) -> (none, none)
+// CHECK-NEXT: %2 = dataflow.carry %phase, %arg4, %15 : i32
+// CHECK-NEXT: %3:2 = dataflow.demux %phase, %2 : (i1, i32) -> (i32, i32)
+// CHECK-NEXT: %4 = dataflow.invariant %phase, %arg1 : i64
+// CHECK-NEXT: %after_cond, %after_value = dataflow.gate %phase, %4 : i64
+// CHECK-NEXT: %5:2 = dataflow.demux %after_cond, %after_value : (i1, i64) -> (i64, i64)
+// CHECK-NEXT: %6 = dataflow.carry %phase, %arg0, %16 : none
+// CHECK-NEXT: %7 = dataflow.carry %phase, %arg0, %16 : none
+// CHECK-NEXT: %8:2 = dataflow.demux %phase, %6 : (i1, none) -> (none, none)
+// CHECK-NEXT: %9:2 = dataflow.demux %phase, %7 : (i1, none) -> (none, none)
+// CHECK-NEXT: %10 = arith.index_cast %iv : i64 to index
+// CHECK-NEXT: %11 = arith.index_cast %after_value : i64 to index
+// CHECK-NEXT: %12 = arith.addi %10, %11 : index
+// CHECK-NEXT: %13:2 = dataflow.sync %1#1, %8#1 : (none, none) -> (none, none)
+// CHECK-NEXT: %data, %done = dataflow.load %arg5[%12] %13#0 : memref<?xi32>
+// CHECK-NEXT: %14:2 = dataflow.sync %9#1, %done : (none, none) -> (none, none)
+// CHECK-NEXT: %15 = arith.addi %3#1, %data : i32
+// CHECK-NEXT: %16 = dataflow.store %arg5[%12] %15 %14#0 : memref<?xi32>
+// CHECK-NEXT: %17 = arith.cmpi slt, %arg1, %arg2 : i64
+// CHECK-NEXT: %18:2 = dataflow.demux %17, %1#0 : (i1, none) -> (none, none)
+// CHECK-NEXT: %19:2 = dataflow.sync %18#1, %5#0 : (none, i64) -> (none, i64)
+// CHECK-NEXT: %20 = dataflow.mux %17, %18#0, %19#0 : (i1, none, none) -> none
+// CHECK-NEXT: %21:2 = dataflow.sync %20, %9#0 : (none, none) -> (none, none)
+// CHECK-NEXT: %22:2 = dataflow.sync %21#0, %3#0 : (none, i32) -> (none, i32)
+// CHECK-NEXT: dataflow.graph.return %22#0, %22#1 : none, i32
+// CHECK-NEXT: }
+// CHECK-NEXT: dataflow.graph private @pair_2(%arg0: none, %arg1: i64, %arg2: i64, %arg3: i64, %arg4: memref<?xi32>, %arg5: memref<?xi32>) -> () attributes {input_segments = array<i32: 3, 0, 2>, result_segments = array<i32: 0, 0, 0>} {
+// CHECK-NEXT: %iv, %phase = dataflow.stream %arg1, %arg2, %arg3 step add while slt : i64
+// CHECK-NEXT: %0 = dataflow.carry %phase, %arg0, %1#1 : none
+// CHECK-NEXT: %1:2 = dataflow.demux %phase, %0 : (i1, none) -> (none, none)
+// CHECK-NEXT: %2 = dataflow.carry %phase, %arg0, %9 : none
+// CHECK-NEXT: %3 = dataflow.carry %phase, %arg0, %9 : none
+// CHECK-NEXT: %4:2 = dataflow.demux %phase, %2 : (i1, none) -> (none, none)
+// CHECK-NEXT: %5:2 = dataflow.demux %phase, %3 : (i1, none) -> (none, none)
+// CHECK-NEXT: %6 = arith.index_cast %iv : i64 to index
+// CHECK-NEXT: %7:2 = dataflow.sync %1#1, %4#1 : (none, none) -> (none, none)
+// CHECK-NEXT: %data, %done = dataflow.load %arg5[%6] %7#0 : memref<?xi32>
+// CHECK-NEXT: %8:2 = dataflow.sync %5#1, %done : (none, none) -> (none, none)
+// CHECK-NEXT: %9 = dataflow.store %arg4[%6] %data %8#0 : memref<?xi32>
+// CHECK-NEXT: dataflow.graph.return values() streams() memories() complete(%1#0, %5#0 : none, none)
+// CHECK-NEXT: }
+// CHECK-NEXT: }
+// CHECK-EMPTY: