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input.generic.mlir

"builtin.module"() ({
  "llvm.func"() <{CConv = #llvm.cconv<ccc>, function_type = !llvm.func<vector<4xf32> (vector<4xf32>, vector<4xf32>, vector<4xf32>)>, linkage = #llvm.linkage<external>, sym_name = "f0", unnamed_addr = 0 : i64, visibility_ = 0 : i64}> ({
  ^bb0(%arg3: vector<4xf32>, %arg4: vector<4xf32>, %arg5: vector<4xf32>):
    %2 = "llvm.intr.fmuladd"(%arg3, %arg4, %arg5) <{fastmathFlags = #llvm.fastmath<none>}> : (vector<4xf32>, vector<4xf32>, vector<4xf32>) -> vector<4xf32>
    %3 = "llvm.intr.fmuladd"(%arg3, %arg4, %2) <{fastmathFlags = #llvm.fastmath<contract>}> : (vector<4xf32>, vector<4xf32>, vector<4xf32>) -> vector<4xf32>
    "llvm.return"(%3) : (vector<4xf32>) -> ()
  }) : () -> ()
  "llvm.func"() <{CConv = #llvm.cconv<ccc>, function_type = !llvm.func<vector<4xf32> (vector<4xf32>, vector<4xf32>, vector<4xf32>)>, linkage = #llvm.linkage<external>, sym_name = "f1", unnamed_addr = 0 : i64, visibility_ = 0 : i64}> ({
  ^bb0(%arg0: vector<4xf32>, %arg1: vector<4xf32>, %arg2: vector<4xf32>):
    %0 = "llvm.fmul"(%arg0, %arg1) <{fastmathFlags = #llvm.fastmath<none>}> : (vector<4xf32>, vector<4xf32>) -> vector<4xf32>
    %1 = "llvm.intr.fmuladd"(%arg0, %arg1, %arg2) <{fastmathFlags = #llvm.fastmath<nnan, contract>}> : (vector<4xf32>, vector<4xf32>, vector<4xf32>) -> vector<4xf32>
    "llvm.return"(%1) : (vector<4xf32>) -> ()
  }) : () -> ()
}) : () -> ()